Multiple Scan Tree Design with Test Vector Modification

Miyase, Kohei; Kajihara, Seiji; Reddy, S.M.

doi:10.1109/ats.2004.61

Cited by 25 publications

(6 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Scan re-architecture is to sequence and arrange the registers in the chain in order to reduce test application time, which blacks whole part according to different function of whole circuit called over lop test system method in the paper [7], [8], [9]. The method is to arrange those registers by usage frequency are higher possibly close to the output port or input port of scan chain, usage frequency of registers is correspond with the number of test vectors of each part.…”

Section: Single Full Scan With Function Of Multi-chainsmentioning

confidence: 99%

Testability design of motor control digital signal processor

Yan

2010

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

View full text Add to dashboard Cite

According to architecture characteristics of the motor control digital signal processor (MCDSP), we select standard boundary scan test which is compatible with IEEE 1149.1 as main method, and full scan test as complementary method to test whole chip. Adopted self-definition address registers, data registers, control registers together, boundary scan test makes the use of the original core circuit of MCDSP, and uses MARCH B algorithm to test RAM, ROM and registers stacks, reducing the hardware expense; full scan technique establishes a single scan chain which has function of multi-chains, reducing test application time. Compared to traditional test methods, the combined methods come to a good equilibrium between hardware expense and test application time.

show abstract

Section: Single Full Scan With Function Of Multi-chainsmentioning

confidence: 99%

Testability design of motor control digital signal processor

Yan

2010

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

View full text Add to dashboard Cite

show abstract

“…It will make aliasing happen easily during compaction and be hard to design a compactor. To resolve such a problem, [15] extended the concept of compatibilities in [11][12][13][14], and proposed an extended compatibility scan tree construction. This method can reduce test application time and test power effectively.…”

Section: A Extended Compatibility Scan Treementioning

confidence: 99%

A response compactor for extended compatibility scan tree construction

You

Huang

Inoue

et al. 2009

2009 IEEE 8th International Conference on ASIC

View full text Add to dashboard Cite

“…In scan tree techniques [15][16][17][18][19][20] , scan cells are constructed into a tree structure. Test application time, test data volume and test power [19,20] are reduced.…”

Section: Introductionmentioning

confidence: 99%