Multiplier-Less Stream Processor for 2D Filtering in Visual Search Applications

Licciardo, Gian Domenico; Cappetta, Carmine; Benedetto, Luigi Di; Rubino, Alfredo; Liguori, Rosalba

doi:10.1109/tcsvt.2016.2603068

Cited by 34 publications

(10 citation statements)

References 21 publications

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“…Besides the above discussed CLB based image buffering schemes, few other embedded BRAM based image buffering schemes have also been reported in literature [12], [13], [18], [6], [20], [21]. Liang et al [12] theoretically proposed full parallel buffering scheme by using BRAMs.…”

Section: Relevant Workmentioning

confidence: 99%

“…However, in this work BRAM has been employed as FIFOs and in this way, were not able to utilize the full storage capacity of BRAM. Michael Schmidt et al [13], Moore [18], Licciardo et al [20], [21]. have also implemented FB by using sequential BRAMs.…”

Section: Relevant Workmentioning

confidence: 99%

“…Therefore, overall resource consumption of these buffering schemes is considerably high. On the other hand, the BRAM based buffers [12], [13], [18], [6], [21] are also resource inefficient as they occupy one BRAM per image row. For example, the frequently used 320×256 gray scale images require only 2.5…”

Section: Relevant Workmentioning

confidence: 99%

“…The conventional on-chip data buffers can be divided into two main groups: Partial Buffers (PBs) [7] - [11], [9] and Full Buffers (FBs) [5], [7], [12], [20], [21] . The PBs [7] - [11] store only partial input image pixels, and therefore they are resource efficient but their bandwidth requirement increases proportionally with the window (kernel) size.…”

Section: Introduction R Ecent Technological Advancements Open New mentioning

confidence: 99%

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Resource-Efficient Image Buffer Architecture for Neighborhood Processors

et al. 2020

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Neighborhood image processing operations on Field Programmable Gate Array (FPGA) are considered as memory intensive operations. Large memory bandwidth is required to transfer the required pixel data from external memory to the processing unit. On-chip image buffers are employed to reduce this data transfer rate. Conventional image buffers, implemented either by using FPGA logic resources or embedded memories are resource inefficient. They exhaust the limited FPGA resources quickly. Consequently, hardware implementation of neighborhood operations becomes expensive, and integrating them in resource constrained devices becomes unfeasible. This paper presents a resource efficient FPGA based on-chip buffer architecture. The proposed architecture utilizes full capacity of a single Xilinx Block-RAM (BRAM36 primitive) for storing multiple rows of input image. To get multiple pixels/clock in a user defined scan order, an efficient duty-cycle based memory accessing technique is coupled with a customized addressing circuitry. This accessing technique exploits switching capabilities of BRAM to read 4 pixels in a single clock cycle without degrading system frequency. The addressing circuitry provides multiple pixels/clock in any user defined scan order to implement a wide range of neighborhood operations. With the saving of 83% BRAM resources, the buffer architecture operates at 278 MHz on Xilinx Artix-7 FPGA with an efficiency of 1.3 clock/pixel. It is thus capable to fulfill real time image processing requirements for HD image resolution (1080×1920) @103 fps.

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Section: Relevant Workmentioning

confidence: 99%

Section: Relevant Workmentioning

confidence: 99%

Section: Relevant Workmentioning

confidence: 99%

Section: Introduction R Ecent Technological Advancements Open New mentioning

confidence: 99%

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Resource-Efficient Image Buffer Architecture for Neighborhood Processors

et al. 2020

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“…The aim of the present work is to develop a novel 2D convolutional filter for the processing of images obtaining FP32 results, showing low area occupation and power consumption, while achieving good speed performances. This has been achieved exploiting an ad hoc partitioning method of the operands [15,16], dedicated to multimedia applications and to all other applications which present a well-defined integer input range and working on kernels of fixed coefficients. Moreover, the design is capable of working on continuous data streams, which could be provided by either an external memory or an acquisition device, such as an image sensor without using any frame buffer, thanks to a careful organization and management of small intermediate buffers, which allow for on-the-fly calculations.…”

Section: Introductionmentioning

confidence: 99%

Design of a Convolutional Two-Dimensional Filter in FPGA for Image Processing Applications

2017

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Exploiting the Bachet weight decomposition theorem, a new two-dimensional filter is designed. The filter can be adapted to different multimedia applications, but in this work it is specifically targeted to image processing applications. The method allows emulating standard 32 bit floating point multipliers using a chain of fixed point adders and a logic unit to manage the exponent, in order to obtain IEEE-754 compliant results. The proposed design allows more compact implementation of a floating point filtering architecture when a fixed set of coefficients and a fixed range of input values are used. The elaboration of the data proceeds in raster-scan order and is capable of directly processing the data coming from the acquisition source thanks to a careful organization of the memories, avoiding the implementation of frame buffers or any aligning circuitry. The proposed architecture shows state-of-the-art performances in terms of critical path delay, obtaining a critical path delay of 4.7 ns when implemented on a Xilinx Virtex 7 FPGA board

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