Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS

Bos, Lynn; Vandersteen, Gerd; Rombouts, Pieter; Geis, Arnd; Morgado, Alonso; Rolain, Yves; Plas, G. Van der; Ryckaert, Julien

doi:10.1109/jssc.2010.2046240

Cited by 46 publications

(21 citation statements)

References 25 publications

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“…Ideally, the modulator is able to digitize signals with B w from 5MHz to 60MHz and an effective resolution ranging from 9 to 16 bits. According to (8), these specifications can be satisfied for OSR 1 ∈ [8,128] and p = [2,3,4,5,6]. This is illustrated in Fig.…”

Section: Finite Gbw Errormentioning

confidence: 98%

“…using a multi-rate system [7]. This approach has been applied to both DT- [8] and CT-ΣΔMs [9]. However, in both cases, the strategy was based on using a lower OverSampling Ratio (OSR) in the front-end parts of the modulator -where most of the power is consumed -and a higher OSR in the subsequent stages or blocks -where the dynamic requirements can be relaxed.…”

Section: Introductionmentioning

confidence: 99%

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Efficient Multi-rate Hybrid Continuous-Time/Discrete-Time Cascade 2-2 Sigma-Delta Modulators for Wideband Telecom

Garcia-Sanchez

Rosa

2012

VLSI-SoC: Advanced Research for Systems on Chip

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Abstract. This chapter discusses the use of hybrid continuous-time /discrete-time fourth-order cascade two-stage 2-2 ΣΔ modulators for wideband low-power wireless applications. The modulator architecture under study is based on a new concept of multi-rate operation, in which the front-end stage -implemented using continuous-time (Gm-C) integrators -operates at a higher rate than the back-end (switched-capacitor) stage. This strategy benefits from the faster operation of continuous-time circuits while keeping power efficiency and high robustness against circuit element tolerances. A comparison with conventional multi-rate and single-rate (continuous-time) ΣΔ modulators is carried out based on the impact of main circuit-level error mechanisms, namely: mismatch, finite OTA dc gain and finite gain-bandwidth product. Closed-form analytical expressions are derived for the nonideal in-band noise power of the different architectures under study, demonstrating a good agreement with simulations and showing the benefits of the presented approach. Simulation results show that the proposed modulator is able to operate with a maximum sampling rate of up to 1GHz, digitizing signals with a 44-to-92dB peak signal-to-(noise+distortion) ratio within a programmable 5-to-60MHz bandwidth.

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Section: Finite Gbw Errormentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

Efficient Multi-rate Hybrid Continuous-Time/Discrete-Time Cascade 2-2 Sigma-Delta Modulators for Wideband Telecom

Garcia-Sanchez

Rosa

2012

VLSI-SoC: Advanced Research for Systems on Chip

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“…[13][14][15][16][17][18] In a high-order modulator, NTF parameters should be carefully selected to ensure the stability of the whole system. For this reason, a fourth-order Butterworth transfer function of a low-pass filter is used to make the modulator stable.…”

Section: System Designmentioning

confidence: 99%

A 16-bit sigma-delta ADC applied in micro-machined inertial sensor

Liu

2015

AIP Advances

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“…Therefore, their integrator coefficients need to be changed depending on the clock frequency. On the contrary, switched-capacitor (SC) reconfigurable ΔΣΜs do not suffer from this and their corresponding poles and zeros of the NTF scale automatically with the clock frequency [8]. SC modulators can thus be clocked at virtually any rate allowed by the gain-bandwidth product of the opamps that they use.…”

Section: Introductionmentioning

confidence: 99%

A design methodology for power‐efficient reconfigurable SC ΔΣ modulators

Porrazzo

Morgado

Bello

et al. 2014

Circuit Theory & Apps

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SUMMARYThis paper presents a methodology to design reconfigurable switched-capacitor (SC) delta-sigma modulators Ms) capable of keeping their corresponding power efficiency figures constant and optimal for a set of resolutions and signal bandwidths. This method is especially suitable for lowbandwidth, medium-to-high resolution specifications, which are common in bio-medical application range. The presented methodology is based on an analytic model of all different contributions to the power dissipation of the ΔΣM. In particular, a novel way to predict the static power dissipated by integrators based on class-A and class-AB OTAs is presented. The power-optimal solution is found in terms of filter order, quantizer resolution, oversampling ratio and capacitor dimensions for a targeted resolution and bandwidth. As the size of the sampling capacitors is crucial to determine power consumption, three approaches to achieve reconfigurability are compared: sizing the sampling capacitors to achieve the highest resolution and keep them constant, change only the first sampling capacitor according to the targeted resolution or program all sampling capacitors to the required resolution. The second approach results in the best trade-off between power efficiency and simplicity. A reconfigurable ΔΣM for bio-medical applications is designed at transistor-level in a 0.18μm CMOS process following the methodology discussed. A comparison between the power estimated by the proposed analytic model and the transistor implementation shows a maximum difference of 17%; validating thus the proposed approach.

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Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS

Cited by 46 publications

References 25 publications

Efficient Multi-rate Hybrid Continuous-Time/Discrete-Time Cascade 2-2 Sigma-Delta Modulators for Wideband Telecom

Efficient Multi-rate Hybrid Continuous-Time/Discrete-Time Cascade 2-2 Sigma-Delta Modulators for Wideband Telecom

A 16-bit sigma-delta ADC applied in micro-machined inertial sensor

A design methodology for power‐efficient reconfigurable SC ΔΣ modulators

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