Nanoprobing on the SRAM static noise margin (SNM) soft fail analysis

Chen, C. Q.; Ng, P.T.; Rivai, Francis; Z., Y.; Tan, Puay Siew; Tan, H.; Lam, Jeffrey; H., Z.

doi:10.1109/ipfa.2016.7564248

Cited by 5 publications

(2 citation statements)

References 3 publications

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“…For SRAM, the static noise margin (SNM) in different operation modes and the dynamic read stability time are generally regarded as the key performance factors. [26][27][28][29] Thus, parasitic RC effects on the 6T-SRAM are emphasized through the analysis of these factors. For static noise margin analysis, Fig.…”

Section: Discussion On Parasitic Effects In 6t-srammentioning

confidence: 99%

Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

Huang¹,

Meng²,

King³

et al. 2017

Jpn. J. Appl. Phys.

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A thorough investigation of the parasitic resistance and capacitance (RC) effects of a single-fin FinFET on logic CMOS devices and circuits is presented. As parasitic RC effects become increasingly prominent in nanoscaled FinFET technologies, they are critical to the overall device and circuit performance. In addition, the effects of dummy patterns as well as multifin structures are analyzed and modeled in detailed. By incorporating parasitic resistance and capacitance extracted by both measurement and simulation, the static and dynamic performance characteristics of standard six transistor static random-access memory (6T-SRAM) cells are comprehensively evaluated as an example of parasitic RC effects in this investigation.

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Section: Discussion On Parasitic Effects In 6t-srammentioning

confidence: 99%

Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

Huang¹,

Meng²,

King³

et al. 2017

Jpn. J. Appl. Phys.

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“…Te size of memory cell is mainly related to its stability, and the noise margin is an important parameter for the stable storage of data in the memory cell. Te noise margin of nvSRAM mainly includes static noise margin (SNM) [10], read noise margin (RNM) [11][12][13], and write noise margin (WNM) [14]. Te three-noise margin represents the antinoise ability of the memory cell in three modes: data storage, reading, and writing.…”

Section: Memory Cell Size Analysismentioning

confidence: 99%

A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node

Yin

Liao

Chen

2023

Active and Passive Electronic Components

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Combining with a static random-access memory (SRAM) and resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell is proposed in this study. With differential mode, a pair of 1T1R RRAM is added to 6T SRAM storage node. By optimizing the connection and layout scheme, the power consumption is reduced and the data stability is improved. The nvSRAM memory cell is realized with UMC CMOS 28 nm 1p9m process. When the power supply voltage is 0.9 V, the static noise/read/write margin is 0.35 V, 0.16 V, and 0.41 V, respectively. The data storage/restoration time is 0.21 ns and 0.18 ns, respectively, with an active area of 0.97 μm2.

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Embed SRAM IDDOFF fail root cause identification by combination of device analysis and localized circuit analysis

Chen

Ang

et al. 2017

Microelectronics Reliability

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Nanoprobing on the SRAM static noise margin (SNM) soft fail analysis

Cited by 5 publications

References 3 publications

Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node

Embed SRAM IDDOFF fail root cause identification by combination of device analysis and localized circuit analysis

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