Negative bias temperature instability (NBTI) in deep sub-micron p/sup +/-gate pMOSFETs

A comparison of plasma-induced damage on the reliability between high-k/metal-gate and SiO2/poly-gate complementary metal oxide semiconductor technology

“…In summary, the results of Figs. [8][9][10][11][12] show that the transient nature of the damage-enhanced electron trapping in high-k film affects the NMOFETs' PBTI and PMOSFETs' NBTI performance, consistent with the damage model of high-k/metal-gate CMOS technology proposed in this study.…”

“…For SiO 2 /poly-gate PMOSFETs experiencing NBTI, holes in the inversion layer gain sufficient energy to dissociate the weak Si-H bonds. This in turn generates interface states with holes (positive charges) trapped in the SiO 2 /Si-substrate interface [10] as shown in Fig. 7.…”

“…Therefore, not only the process but also the electrical reliability of the high-k/metal-gate transistors must be compatible with current SiO 2 /poly-gate CMOS technology [9]. Previous studies on p-channel PMOSFETs have shown that positive charges (holes) become trapped at the SiO 2 / Si-substrate interface under negative gate bias stress, causing shifts in the threshold voltage (V TH ) during prolonged device operation (i.e., negative bias temperature instability (NBTI) effect) [10,11]. Electrons trapped in oxygen vacancies in high-k film for n-channel MOSFETs (NMOSFETs), cause a significant shift in V TH under positive gate bias stress (i.e., positive bias temperature instability (PBTI) effect [12].…”