New considerations for MOSFET power clamps

Poon, Steven S.S.; Maloney, Timothy J.

doi:10.1016/s0026-2714(03)00123-9

Cited by 38 publications

(20 citation statements)

References 3 publications

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“…Recently, some work has been reported on how to reduce the gate leakage current for digital circuits in advanced CMOS processes [11], [12]. In the traditional power-rail ESD clamp circuit which is used to protect the core circuits [13], the large-sized ESD clamp device and the MOS capacitor will suffer serious gate leakage problem and induce huge whole-chip standby leakage current while implementing in nanoscale CMOS process [14]. New designs on the power-rail ESD clamp circuit should be developed to further reduce such standby leakage current in nanometer CMOS processes.…”

Section: * This Work Was Supported By Ministry Of Economic Affairs Tmentioning

confidence: 99%

“…To solve the problem of malfunction in the traditional RCbased ESD detection circuit [13], the timer level restorer was ever reported [14]. However, even with the additional timer level restorer, the gate current of ESD clamp MOSFET and MOS capacitor still result in a total standby leakage current of several ten micro-amperes at 125°C in a 130nm CMOS process.…”

Section: Esd Clamp Circuit With Consideration Of Gate Leakage Curmentioning

confidence: 99%

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Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS

Ker

Wang

2009

2009 IEEE Custom Integrated Circuits Conference

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Electrostatic discharge (ESD) protection for mixedvoltage I/O interfaces has been one of the major challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. Moreover, the gate leakage current across thin gateoxide devices has serious degradation on circuit performance while circuits implementing in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O buffers should meet the gate-oxide reliability constraints and be designed with consideration of gate leakage current. This paper presents the effective ESD protection scheme with circuit solutions to protect the mixed-voltage I/O buffers in nanoscale CMOS processes against ESD stresses. The proposed ESD protection scheme and the specific ESD clamp circuits with low standby leakage current have been successfully verified in nanoscale CMOS processes. Effective on-chip ESD protection scheme should be early planed and started in the beginning phase of chip design in order to achieve good enough ESD robustness for IC products.

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Section: * This Work Was Supported By Ministry Of Economic Affairs Tmentioning

confidence: 99%

Section: Esd Clamp Circuit With Consideration Of Gate Leakage Curmentioning

confidence: 99%

Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS

Ker

Wang

2009

2009 IEEE Custom Integrated Circuits Conference

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“…Furthermore, the large gate leakage current consumes much power consumption [1][2] and may even cause logic error in operation. Therefore, the gate leakage current must be considered as an urgent task in nanoscale CMOS process.…”

Section: Introductionmentioning

confidence: 99%

A modified ESD clamp circuit for 90-nm CMOS process

Liu

Yang

Luo³

et al. 2012

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology

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In nanoscale CMOS process, integrated circuits (ICs) face serious gate reliability issues such as the damage of electrostatic discharge (ESD). The RC-triggered silicon-controlled rectifier (SCR) is widely studied for the high turn-on efficiency and discharge capability. However, the large gate leakage current of MOS capacitor in the traditional RC network in nanoscale process is not desired. In this work, a modified detection circuit with feedback technique is proposed. The leakage current is reduced to 16 nA at room temperature (25 °C). Under the ESD event, it injects 38 mA trigger current into the p-substrate of SCR. Compared with the previous circuits, the proposed circuit can save area and power consumption while achieving the same performance. The simulation result shows that this clamp circuit can be used in industry.

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“…Each ESD stress at the mixed-voltage I/O pad, ESD bus, VDD, or VSS line has the corresponding well-designed ESD discharging path in this scheme. Besides, some ESD protection designs with highvoltage tolerance have also been studied [6]- [8].…”

Section: Introductionmentioning

confidence: 99%

2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process

Lin

Ker

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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With the consideration of low standby leakage in nanoscale CMOS processes, a new 2×VDD-tolerant ESD clamp circuit was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of the silicon-controlled-rectifier-based (SCRbased) ESD device. This design had been successfully verified in a 65-nm CMOS process. The leakage current of this ESD clamp circuit under normal circuit operating condition was only ~200 nA. Besides, this ESD clamp circuit can achieve 4.8-kV HBM ESD robustness. Therefore, this design was very suitable for mixed-voltage I/O interfaces in nanoscale CMOS processes.

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New considerations for MOSFET power clamps

Cited by 38 publications

References 3 publications

Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS

Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS

A modified ESD clamp circuit for 90-nm CMOS process

2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process

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New considerations for MOSFET power clamps

Cited by 38 publications

References 3 publications

Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS

Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS

A modified ESD clamp circuit for 90-nm CMOS process

2&#x00D7;VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process

Contact Info

Product

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2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process