Non-Alloyed Ohmic Contacts to n-GaAs Using Compositionally Graded In<sub>x</sub>Ga<sub>1-x</sub>As Layers

Nittono, T.; Itô, Hiroshi; Nakajima, O.; Ishibashi, Tadao

doi:10.1143/jjap.27.1718

Cited by 48 publications

(23 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, the lowest demonstrated value of ρ c has been by Nittono et al [30], who achieved a value of 5 × 10 −9 Ω · cm 2 by grading the contact layer to pure InAs. Grading the contact layer eliminates the internal potential barrier in the contact, thus reducing the contact resistance.…”

Section: Source-resistance Scalingmentioning

confidence: 98%

A Self-Aligned InGaAs HEMT Architecture for Logic Applications

Waldron

Kim

Alamo

2010

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

Abstract-In this paper, we present a novel self-aligned process for future III-V logic FETs. Using this process, we have demonstrated enhancement-mode 90-nm-gate-length InGaAs HEMTs with excellent logic figures of merit. We have carried out a detailed analysis of this device architecture to determine its future scaling capabilities. We find that, as the insulator is scaled to achieve enhancement mode, the performance of the device is limited by degradation of the I ON /I OFF ratio due to gate leakage current. By use of TLM test structures, we have determined that the barrier resistance dominates the source resistance. We use a trilayer TLM model to predict the expected evolution of the contact resistance as it is scaled to realistic VLSI dimensions and find that the current technology results in resistance values that are two orders of magnitude higher than the desired target for sub-22-nm nodes. Using the model, we explore different options for device redesign. Both I ON /I OFF and source-resistance limitations imply that the use of a high-k gate dielectric will be required for future device implementations.

show abstract

Section: Source-resistance Scalingmentioning

confidence: 98%

A Self-Aligned InGaAs HEMT Architecture for Logic Applications

Waldron

Kim

Alamo

2010

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

show abstract

“…24 This was expected as InAs, the lowest band gap semiconductor of In x Ga 1Àx As, was employed. Nevertheless, their work may be relevant to inversion-channel InGaAs MOSFET with a low Ohmic contact resistivity being obtained using the regrown InAs.…”

Section: Introductionmentioning

confidence: 94%

Optimization of Ohmic metal contacts for advanced GaAs-based CMOS device

Chang

Chiang

Lin

et al. 2012

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

View full text Add to dashboard Cite

show abstract

“…For HBTs, shallow, non-alloyed contacts are also needed due to decreasing base thicknesses. 4 There are many reports of non-alloyed Ti-based ohmic contacts to n þ -InGaAs (doping up to 5 Â 10 19 cm À3 ) 7-10 prepared with NH 4 OH or dilute acid pre-metallization surface treatments, resulting in q c % 2 Â 10 À7 X-cm 2 with good stability below 300 C. Alternatively, TiW-, 11,12 Mo-, [13][14][15] Pd-, 16 WSi-, 17,18 and ErAs-based 19 ohmic contacts have been studied. Mo has emerged as a good candidate for contacting n þ -InGaAs because of its high melting point and relative ease of deposition.…”

Section: Introductionmentioning

confidence: 99%

Characterization of low-resistance ohmic contacts to n- and p-type InGaAs

Lin

Mohney

2013

Journal of Applied Physics

View full text Add to dashboard Cite

Multilayer ohmic contacts with differing first metal layers (M = Mo, Pd, Pt) beneath a Ti/Pt diffusion barrier and Au cap were fabricated on n+ and p+-InGaAs, and the relationship between their specific contact resistance and interfacial chemistry was examined. Palladium-based contacts offered the lowest specific contact resistances of ρc=3.2×10−8 and 1.9×10−8 Ω-cm2 to n+- and p+-InGaAs, respectively. The low resistances of the Pd-based contact were correlated with the formation of a uniform PdxInGaAs phase in direct contact with InGaAs, as observed using transmission electron microscopy and energy dispersive spectroscopy. On the other hand, the Mo-based contact to n+ and p+-InGaAs had much higher specific contact resistances, even though its specific contact resistance on lightly doped n-InGaAs was nearly the same as that of the Pd-based contact. The cause of this discrepancy was identified to be the native oxide layer that remained between the contact and semiconductor in the Mo-based contacts, as revealed using transmission electron microscopy, energy dispersive spectroscopy, and electron energy loss spectroscopy. The effect of the native oxide in series with the Schottky barrier is significant only when the contact is doped heavily enough that tunneling of carriers through the Schottky barrier introduces a very low resistance.

show abstract

Non-Alloyed Ohmic Contacts to n-GaAs Using Compositionally Graded In_xGa_1-xAs Layers

Cited by 48 publications

References 16 publications

A Self-Aligned InGaAs HEMT Architecture for Logic Applications

A Self-Aligned InGaAs HEMT Architecture for Logic Applications

Optimization of Ohmic metal contacts for advanced GaAs-based CMOS device

Characterization of low-resistance ohmic contacts to n- and p-type InGaAs

Contact Info

Product

Resources

About

Non-Alloyed Ohmic Contacts to n-GaAs Using Compositionally Graded InxGa1-xAs Layers

Cited by 48 publications

References 16 publications

A Self-Aligned InGaAs HEMT Architecture for Logic Applications

A Self-Aligned InGaAs HEMT Architecture for Logic Applications

Optimization of Ohmic metal contacts for advanced GaAs-based CMOS device

Characterization of low-resistance ohmic contacts to n- and p-type InGaAs

Contact Info

Product

Resources

About

Non-Alloyed Ohmic Contacts to n-GaAs Using Compositionally Graded In_xGa_1-xAs Layers