Nonlinear analog DC fault simulation by one-step relaxation

Tian, M.W.; Shi, C.-J.R.

doi:10.1109/vtest.1998.670859

Cited by 15 publications

(12 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The work of [11] presents an example of fault simulation in nonlinear circuits when DC point of the faulty and fault-free circuits are equal. A relaxation technique for fast calculating DC point of nonlinear faulty circuits is discussed in [12]. Examples of fast fault simulators for transient analysis in linear circuits are DRAFTS and FLYER [13] [14].…”

Section: Previous Workmentioning

confidence: 99%

Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example

Hashempour

Dohmen

Tasic

et al. 2011

2011 Design, Automation &Amp; Test in Europe

View full text Add to dashboard Cite

We present an application of Defect Oriented Testing (DOT 1 ) to an industrial mixed signal device to reduce test time and maintain quality. The device is an automotive IC product with stringent quality requirements and a mature test program that is already in volume production. A complete flow is presented including defect extraction, defect simulation, test selection, and validation. A major challenge of DOT for mixed signal devices is the simulation time. We address this challenge with a new fault simulation algorithm that provides significant speedup in the DOT process. Based on the fault simulations, we determine a minimal set of tests which detects all defects. The proposed minimal test set is compared with the actual test results of more than a million ICs. We prove that the production tests of the device can be reduced by at least 35%.

show abstract

Section: Previous Workmentioning

confidence: 99%

Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example

Hashempour

Dohmen

Tasic

et al. 2011

2011 Design, Automation &Amp; Test in Europe

View full text Add to dashboard Cite

show abstract

“…Fault ordering for ease of fault simulation was first proposed by Voorakaranam, Gomes and Chatterjee in [25]. Its use in numerical algorithms for fault simulation was demonstrated by Hou and Chatterjee in [26][27][28] and also used by Tian and Shi in [24]. We first describe the simulation procedure using fault ordering described in [26][27][28].…”

Section: Fault Simulation Based On Partial Numerical Convergencementioning

confidence: 99%

“…This is useful for computing the best stimuli and only one accurate simulation is needed as a post-processing step to calibrate the test procedure after the test is designed. A restricted precedent of the partial numerical circuit solution procedure proposed in this paper, called one-step relaxation has been used for DC fault simulation [24]. However, to the best of our knowledge, this has not been applied to the problem of test generation before.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Test generation for analog circuits using partial numerical simulation

Variyam

Hou²,

Chatterjee³

1999

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)

View full text Add to dashboard Cite

In this paper, we present a novel test generation strategy based on partial numerical fault simulation. Existing fault-based test generation methodologies for analog circuits are based on accurate but expensive fault simulation. In the proposed methodology, fault simulation is terminated before convergence for reasons of simulation speed. The relative fitness of various input stimuli is evaluated based on the results of this partial numerical simulation. A comparison of this new methodology with existing accurate fault simulation based test generation methods, shows up to 15 times speed-up in test generation. IntroductionAlthough there exist fast concurrent and parallel fault simulation algorithms [1,2] and efficient path-based test generation methodologies [3] for digital circuits, fast automatic test generation for analog circuits still poses many barriers that have not been overcome despite intensive research. Analog circuits are typically tested by measuring the circuits specifications. Specification-based testing of analog circuits is expensive and time consuming and the analog and mixed-signal testing community is actively considering the use of fault-based testing similar to that of digital circuits as an alternative. The basic problem with fast fault-based automatic test generation for analog circuits is the lack of fast fault simulation methodologies. Currently, the search for optimum tests during fault-based test generation is performed by invoking existing circuit simulators like HSPICE in a serial manner. Since accurate circuit simulation is CPU-intensive, test generation driven by serial fault simulation (using conventional simulators) is computationally intractable. In this paper, we present a test generation methodology wherein we do not perform accurate fault simulation to drive the search for optimum tests. Instead, we terminate the simulation prior to convergence and evaluate the test stimuli based on the results of partial numerical simulation.Recently, there has been a lot of work in automatic test pattern generation for analog circuits. These test generation schemes can be broadly classified into specification based testing schemes and fault-based testing schemes. In specification-based testing, the performance specifications of the circuit are measured and if any one of them is violated, the circuit under test (CUT) is declared as faulty. Most of the work in specification-based testing has been geared towards eliminating highly correlated tests from a complete set of specification tests [4][5][6][7]. Many other researchers have suggested replacing expensive specification-based tests with low-cost alternate tests [8][9][10][11][12][13].In fault-based testing, functional faults of the CUT are assumed to result from manufacturing and physics-of-failure based defect mechanisms and tests are developed to detect these faults. Defect simulations based on process data are performed on the circuit layout and various defect mechanisms are modeled at the circuit or behavioral level giving a list of pos...

show abstract

“…In the proposed approach, instead of generating a new updated model from scratch, we adopt the matrix inversion formula of Sherman and Morrison as well as the inversion formula of block matrices to efficiently compute the updated Krylov projection subspace [2]. In the past, the Sherman and Morrison inversion formula has been used in [10] for DC fault simulation and in [4] for considering driver resistance variations in interconnect analysis. The dominant computational cost of our approach is due to solving a linear system with M unknowns, where M is equal to the number of circuit nodes if multiple links are inserted or the size of the (small) linear network to be merged.…”

Section: Introductionmentioning

confidence: 99%

Efficient Model Update for General Link-Insertion Networks

Feng

7th International Symposium on Quality Electronic Design (ISQED'06)

View full text Add to dashboard Cite

Link insertion has been proposed as a means of incremental design to improve performance robustness of linear passive networks. In clock network design, links can be inserted between subnetworks to reduce the variability of clock skews introduced by process and environmental fluctuations, thereby improving the network's immunity to PVT variations. Under these scenarios, it is desired to incrementally compute a reduced-order model for the updated network in order to efficiently evaluate the effectiveness of link insertions. In this paper, we present an efficient model update scheme for general link-insertion networks. By updating the Krylov projection subspace used in model order reduction, the proposed scheme can efficiently compute a reduced-order model for the network with inserted links. More generally, we extend the proposed approach to consider the merging of a (small) multiple-input linear network with a much larger network. We demonstrate the usage of the proposed technique for clock networks and general RLC circuits with an arbitrary number of link insertions as well as the more general case where the inserted links are in the form of a linear network.

show abstract

Nonlinear analog DC fault simulation by one-step relaxation

Cited by 15 publications

References 12 publications

Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example

Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example

Test generation for analog circuits using partial numerical simulation

Efficient Model Update for General Link-Insertion Networks

Contact Info

Product

Resources

About