Nonlinearity analysis of resistor string A/D converters

Kuboki, Shigeo; Kato, Katsuji; Miyakawa, Naomichi; Matsubara, Katsumi

doi:10.1109/tcs.1982.1085168

Cited by 25 publications

(15 citation statements)

References 7 publications

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“…The highest timing uncertainty will be in the middle of the VCDL, where the distance to these clean points is highest. This is comparable to mismatch in resistors in a resistor string based A/D converter, where the highest deviation is also found in the middle of the string [18].…”

Section: Dll Output Jitter Due To Delay Cell Mismatchsupporting

confidence: 52%

“…To ease calculations, the noise of the other PLL building blocks is calculated back to the input of the PFD according to (17) the variance of which is referred to as . The PLL jitter due to these noise sources can now be shown to be (setting the other noise sources to zero) (18) Very similarly, the jitter on the reference signal will cause jitter on the PLL output signal, according to (19) Observing these equations leads to the conclusion that, contrary to the VCO induced jitter, a large value of (corresponding to a large PLL bandwidth) will raise the PLL output jitter due to the noise of the other loop components.…”

Section: B Pll Output Jitter Due To Noisementioning

confidence: 98%

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Low-jitter clock multiplication: a comparison between PLLs and DLLs

Beek

Klumperink

Vaucher

et al. 2002

IEEE Trans. Circuits Syst. II

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Abstract-This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output jitter of the architectures, due to the most important noise sources, is presented. Then, another important source of jitter in a DLL-based clock multiplier is treated, namely the stochastic mismatch in the delay cells which compose the DLL voltage-controlled delay line (VCDL). An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. A circuit design technique, called impedance level scaling, is then presented which allows the designer to optimize the noise and mismatch behavior of a circuit, independently from other specifications such as speed and linearity. Applying this technique on a delay cell design yields a direct tradeoff between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage.

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Section: Dll Output Jitter Due To Delay Cell Mismatchsupporting

confidence: 52%

Section: B Pll Output Jitter Due To Noisementioning

confidence: 98%

Low-jitter clock multiplication: a comparison between PLLs and DLLs

Beek

Klumperink

Vaucher

et al. 2002

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

show abstract

“…It has been supposed that this is a variable with a Gaussian pdf. As shown in [12] it is possible to evaluate the pdf of voltage values at every tap of the resistive string from the distributions of resistor values. The pdf of the resistors is a Gaussian distribution with mean value R and variance DR 2 : To calculate the pdf of voltage values it is necessary to do some math on stochastic variables.…”

Section: High-level Model Implementationmentioning

confidence: 99%

High-level modeling of resistor string based digital-to-analog converters

Saponara

Baldetti

Fanucci

et al. 2010

Analog Integr Circ Sig Process

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To obtain a high performance CMOS resistor string digital-to-analog converter (DAC), one of the key design issues is the mismatch in the resistor ratio. This mismatch causes nonlinearity errors such as integral nonlinearity (INL) and differential nonlinearity (DNL), degrading the performances of the converter. Usually these matching properties are taken into account during the design phase by using time consuming and computational intensive transistor-level Monte Carlo simulations for the process technology corner. Recent research aims at reducing the design time by exploiting high-level modeling of converters as a trade-off between simulation time and modelling accuracy. In this work an analytical model for resistor mismatch in DACs is presented and implemented in MATLAB (TM) environment. The model utilizes geometrical size of resistors and statistical data of the technology process. Starting from random process variations on geometries it was possible to estimate DNL and INL with very short time simulations. The proposed model is valid both for single stage resistor string DACs or segmented ones. The model can be used to speed up the design of resistor-string based DACs, or as a starting point to develop more accurate models by taking into account high-order effects. The model was successfully used to design a 10bit resistor string DAC in a 0.18 mu m BCD technology with DNL and INL lower than 1 LSB (in absolute value). Since the complexity of the DAC is dominated by the resistor string, its optimization since the early design steps, enabled by the proposed high-level model, allowed to minimize area versus state of the art

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“…There is no requirement that input signal be random as in [5] because RnDWA takes care of randomization. Based on results of [12], standard deviation of code is (15) where is standard deviation of unit mismatch. It could be shown that average total power of mismatch noise for RnDWA is What this relation shows is the average value of SNR, based on individual unit mismatches; some DACs will show higher or lower SNR.…”

Section: Randomized Dwamentioning

confidence: 99%

Techniques for preventing tonal behavior of data weighted averaging algorithm in /spl Sigma/#x03A3;-/spl Delta/#x0394; modulators

Vadipour

2000

IEEE Trans. Circuits Syst. II

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Two techniques for prevention of in-band tones in DWA mismatch noise shaping algorithm are presented. "Offset technique" moves in-band tones away from baseband, improving SNR by 10 dB, and attenuates maximum in-band tone by as much as 25 dB. "Randomized DWA" is a combination of simultaneous randomization and DWA, which attenuates tonal behavior in all frequencies, preventing aliasing of tones or tone shifting for any arbitrary input signal.Index Terms-A/D and D/A converters, data-weighted averaging, sigma-delta modulators.

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Nonlinearity analysis of resistor string A/D converters

Cited by 25 publications

References 7 publications

Low-jitter clock multiplication: a comparison between PLLs and DLLs

Low-jitter clock multiplication: a comparison between PLLs and DLLs

High-level modeling of resistor string based digital-to-analog converters

Techniques for preventing tonal behavior of data weighted averaging algorithm in /spl Sigma/#x03A3;-/spl Delta/#x0394; modulators

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