2010
DOI: 10.1109/led.2010.2055530
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Nonvolatile Memory With Nitrogen-Stabilized Cubic-Phase $\hbox{ZrO}_{2}$ as Charge-Trapping Layer

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Cited by 27 publications
(22 citation statements)
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“…Having investigated the feasibility to use crystalline ZrO2 as the CTL for flash memory, the comparison of device performance between a crystalline and an amorphous CTL were further studied to better understand how much performance enhancement can be gained by adopting a crystalline CTL [21]. In the study, 3-nm and 17.5-nm SiO2 were respectively used as the tunnel and blocking dielectric while 13-nm ZrON deposited by reactive sputtering of Zr target in a mixture gas ambient of oxygen/nitrogen/argon was adopted as the CTL.…”
Section: (A) Investigating Crystalline Zro2 As Ctl For Si-based Flasmentioning
confidence: 99%
“…Having investigated the feasibility to use crystalline ZrO2 as the CTL for flash memory, the comparison of device performance between a crystalline and an amorphous CTL were further studied to better understand how much performance enhancement can be gained by adopting a crystalline CTL [21]. In the study, 3-nm and 17.5-nm SiO2 were respectively used as the tunnel and blocking dielectric while 13-nm ZrON deposited by reactive sputtering of Zr target in a mixture gas ambient of oxygen/nitrogen/argon was adopted as the CTL.…”
Section: (A) Investigating Crystalline Zro2 As Ctl For Si-based Flasmentioning
confidence: 99%
“…The higher P/E speeds should be due to the higher chargetrapping efficiency of the HfLaON sample with an amorphous HfLaON composite film as the CTL. For the LaON sample, its LaON film shows poly-crystalline structure [5], where the grain boundaries can provide a leakage path to facilitate electrons escaping from the CTL to the gate electrode rather than being trapped in the chargetrapping film, thus leading to a lower trapping efficiency [1], [5]. In addition, due to the shortened tunneling path, the electrons stored in the traps associated with the nonstoichiometric interlayer at the CTL/SiO 2 interface are also easier to escape from the CTL into the Si substrate than those located in the bulk traps [4].…”
Section: Results and Disscusionmentioning
confidence: 99%
“…With an initial ǻV FB of about ~ 3.1 V, the decay rate of the data retention is 65 mV/dec and 80 mV/dec for the HfLaON and LaON samples respectively. The worse data retention of the LaON sample should be ascribed to the poly-crystalline structure of the LaON film, where the electrons trapped along the grain boundaries are easier to escape, thus deteriorating the data retention [1], [5]. Moreover, the formation of La silicate interlayer at the CTL/SiO 2 interface could also contribute to its poor retention property, because the traps associated with the interlayer can accelerate the charge loss [4].…”
Section: Results and Disscusionmentioning
confidence: 99%
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