Novel Back Gate Doping Ultra Low Retention Power 22nm FDSOl SRAM for IOT Application

Chang, Ming Wen; Chan, N.; Joshi, Vivek; Hecker, Sandra; Ziller, Udo; Poth, Petra; Zaka, A.; Herrmann, T.; Seo, Seunghwan; Yoon, Hee-Sun; Zou, Xin; Xu, Ziqiang; Ramamurthy, Hema; Klick, T.; Congedo, G.; Lee, Youmean; Erben, Elke; Zschaetzsch, Gerd; Faul, J.; Kluth, J.; Schmid, J.; vanBentum, R.; Weintraub, C.

doi:10.1109/essderc.2018.8486897

Cited by 2 publications

(4 citation statements)

References 5 publications

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“…Hence, we conclude that the partitioned FECC is a very effective way to lower the DRV. This work shows that advanced design techniques for SRAM can lower memory energy consumption to the levels that are needed for biomedical platforms and eventually other IoT, low energy, applications 2 Suffix P uses a push-rule cell 3 Estimated from graph 4 Prec, at 38 kHz access rate and with size compensation, but only taking the leakage power of the other banks into account, not the dynamic power overhead of the long datalines, crossing multiple banks.…”

Section: Discussionmentioning

confidence: 99%

“…Aggressive stand-by voltage scaling with foundry macros is possible, but limited to around 400mV in 28-22 nm technologies due to local process variation [3], [16], even with the low variation promised in the 22nm FD-SOI technology [9]. In this voltage range, the macros are in near-threshold operation.…”

Section: A Lower Retention Voltagementioning

confidence: 99%

“…Note that [22] is not resized, as it is larger than the required memory. For [4], the operating frequency is too low to meet recording specifications and [1], [3], [16] do not provide the necessary energy numbers for the power estimation. Hence they are not taken into account in the comparison.…”

Section: Poffmentioning

confidence: 99%

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A 1MHz 256kb Ultra Low Power Memory Macro for Biomedical Recording Applications in 22nm FD-SOI Using FECC to Enable Data Retention Down to 170mV Supply Voltage

Vanhoof,

Dehaene

2024

IEEE Trans. Circuits Syst. I

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In biomedical sensor platforms, low energy consumption is of utmost importance to extend battery life. A dominant contributor in the energy budget of such platforms is the always-on recording memory. Hence, a low energy memory is required. This paper implements such a memory with aggressive voltage scaling to run the memory in the sub-threshold region during retention. Fine grained forward error correction is a key enabler for this. It allows operation of the memory beyond the point of first failure and acts similar to EDAC techniques for timing failure detection in voltage-scaled microcontrollers. The memory is embedded in a RISC-V microcontroller and fabricated in a 22nm FDSOI technology. Measurements show an always-on retention voltage down to 170mV, which results in a total average power of only 5.11uW, a 70% reduction compared to the signoff point. The memory is extensively tested with memtest and found to be fully functional up to 1.2 MHz.

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Section: Discussionmentioning

confidence: 99%

Section: A Lower Retention Voltagementioning

confidence: 99%

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A 1MHz 256kb Ultra Low Power Memory Macro for Biomedical Recording Applications in 22nm FD-SOI Using FECC to Enable Data Retention Down to 170mV Supply Voltage

Vanhoof,

Dehaene

2024

IEEE Trans. Circuits Syst. I

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“…More than half of the energy budget is due to memory [5], [6]. Bearing in mind the low-speed recording application, the use of a lower-voltage custom SRAM is preferred over a high-speed foundry SRAM [7], [8]. However, aggressive voltage scaling requirements tend to dramatically increase transistor variation.…”

Section: Introductionmentioning

confidence: 99%

SRAM With Stability Monitoring and Body Bias Tuning for Biomedical Applications

Vanhoof

Dehaene

2022

IEEE Solid-State Circuits Lett.

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This work presents a novel low leakage SRAM architecture with always-retention and local wake-up. To tackle the large design margins in deep sub-micron technology nodes, it includes SNM monitoring and compensation circuitry to track variation across the memory array. This allows for operation close to the point of first failure. As proof of concept, a macro of 1Mbit is fabricated in 22nm FDSOI. Measurements show an active energy of 3.6 pJ/access at 6.6 MHz and a leakage power of 0.19 pW/cell, a reduction of 53.8% due to margin reduction.

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Novel Back Gate Doping Ultra Low Retention Power 22nm FDSOl SRAM for IOT Application

Cited by 2 publications

References 5 publications

A 1MHz 256kb Ultra Low Power Memory Macro for Biomedical Recording Applications in 22nm FD-SOI Using FECC to Enable Data Retention Down to 170mV Supply Voltage

A 1MHz 256kb Ultra Low Power Memory Macro for Biomedical Recording Applications in 22nm FD-SOI Using FECC to Enable Data Retention Down to 170mV Supply Voltage

SRAM With Stability Monitoring and Body Bias Tuning for Biomedical Applications

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