Novel bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced isolation (SITOS) and gate to shallow-well contact (SSS-C) processes for ultra low power dual gate CMOS

Kotaki, Hiroshi; Kakimoto, S.; Nakano, M.; Matsuoka, Toshimasa; Adachi, K.; Sugimoto, K.; Fukushima, Takashi; Sato, Yasuhiro

doi:10.1109/iedm.1996.553626

Cited by 26 publications

(7 citation statements)

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“…By introducing a narrow bandgap SiGe layer for the channel region, a reduction of can be achieved while keeping high impurity doping level at the body region. Such a highly doped body is effective for suppressing the short channel effect and reducing the body resistance that is a cause of propagation delay in the SOI DTMOS [3]. A higher drive current can be also expected utilizing the enhanced hole mobility in the SiGe channel.…”

Section: Sige Hdtmosmentioning

confidence: 96%

A novel high performance SiGe channel heterostructure dynamic threshold pMOSFET (HDTMOS)

Takagi

Inoue

Hara

et al. 2001

IEEE Electron Device Lett.

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In this letter, we propose a novel SiGe channel heterostructure dynamic threshold metal oxide semiconductor (DTMOS) and demonstrate its superiority over conventional Si-DTMOS. The introduction of a SiGe layer for the channel is very effective for reducing the threshold voltage in spite of keeping impurity doping level at the body region. Therefore, a low threshold voltage and a large body effect factor can be achieved simultaneously. The SiGe HDTMOS with highly doped body exhibits 2 times higher transconductance, 1.4 times higher saturation current, and better short channel immunity than that of the control Si-DTMOS with lightly doped body of which threshold voltage is nearly the same.Index Terms-, body effect factor, DTMOS, parasitic channel, short channel effect, SiGe.

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Section: Sige Hdtmosmentioning

confidence: 96%

A novel high performance SiGe channel heterostructure dynamic threshold pMOSFET (HDTMOS)

Takagi

Inoue

Hara

et al. 2001

IEEE Electron Device Lett.

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“…Isolation comes naturally for DTMOS when implemented on SOI wafers but is quite difficult for bulk silicon wafers. Reference [17] presented the first bulk DTMOS results using 1.5-m trenches and a four-well process-not a small task for most fabs. Other bulk-Si DTMOS options are currently being investigated.…”

Section: Process Issuesmentioning

confidence: 99%

Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages

Lindert

Sugii

Tang

et al. 1999

IEEE J. Solid-State Circuits

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We have investigated circuit options to surpass the 1-V power-supply limitation predicted by traditional scaling guidelines. By modulating the body bias, we can dynamically adjust the threshold voltage to have different on-and off-state values. Several dynamic threshold voltage MOSFET (DTMOS) logic styles were analyzed for ultralow-power use-from 1.5 down to 0.5 V. Since ordinary pass-transistor logic degrades as the voltages are reduced, we investigated the effects that a dynamic threshold has on various styles of pass-transistor logic. Three different pass-transistor restoration schemes were simulated with the various DTMOS techniques. Results indicate that controlling the body bias can provide a substantial speed increase and that such techniques are useful over a large range of supply voltages. Process complexity and other tradeoffs associated with DTMOS logic variations are also discussed.

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“…The DTMOS scheme thus appears to be very promising for future low-power and high-speed circuit applications, since it improves the circuit speed without compromising the stand-by power. Previously reported DTMOS's, however, suffer from a small body-effect-factor ( ) [7]. This is because the normal suitable for low operation is usually too small to be compatible with a high substrate doping concentration, resulting in a low .…”

Section: Introductionmentioning

confidence: 99%

“…This is because the normal suitable for low operation is usually too small to be compatible with a high substrate doping concentration, resulting in a low . A low prevents the DTMOS from enjoying a large reduction in the on-state, thus minimizes its gain in on-state current-drive during DTMOS-mode operation [7]- [10]. Recently, we have proposed a new DTMOS using an SSR channel profile by indium implantation to overcome the above shortcomings [11].…”

Section: Introductionmentioning

confidence: 99%

high-performance and high-reliability 80-nm gate-length DTMOS with indium super steep retrograde channel

Chang

Chen

et al. 2000

IEEE Trans. Electron Devices

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In this paper, we demonstrate for the first time a high-performance and high-reliability 80-nm gate-length dynamic threshold voltage MOSFET (DTMOS) using indium super steep retrograde channel implantation. Due to the steep indium super steep retrograde (In-SSR) dopant profile in the channel depletion region, the novel In-SSR DTMOS features a low in the off-state suitable for low-voltage operation and a large body effect to fully exploit the DTMOS advantage simultaneously, which is not possible with conventional DTMOS. As a result, excellent 80-nm gate length transistor characteristics with drive current as high as 348 A/ m (off-state current 40 nA/ m), a record-high = 1022 mS/mm, and a subthreshold slope of 74 mV/dec, are achieved at 0.7 V operation. Moreover, the reduced body effects that have seriously undermined conventional DTMOS operation in narrow-width devices are alleviated in the In-SSR DTMOS, due to reduced indium dopant segregation. Finally, it was found for the first time that hot-carrier reliability is also improved in DTMOS-mode operation, especially for In-SSR DTMOS. Index Terms-DTMOS, indium, super-steep-retrograde (SSR) channel.

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Novel bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced isolation (SITOS) and gate to shallow-well contact (SSS-C) processes for ultra low power dual gate CMOS

Cited by 26 publications

References 0 publications

A novel high performance SiGe channel heterostructure dynamic threshold pMOSFET (HDTMOS)

A novel high performance SiGe channel heterostructure dynamic threshold pMOSFET (HDTMOS)

Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages

high-performance and high-reliability 80-nm gate-length DTMOS with indium super steep retrograde channel

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