2009 IEEE/SEMI Advanced Semiconductor Manufacturing Conference 2009
DOI: 10.1109/asmc.2009.5155979
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Novel in-line inspection method for non-visual defects and charging

Abstract: Surface potential difference (SPD) measurements have shown to be effective in in-line characterizing charging non-uniformity and non-visual residues for both process and tool development but also in in-line characterizing properties of ultra thin transistor work function layers

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Cited by 4 publications
(3 citation statements)
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“…Recently, Characterizing charging non-uniformity and non-visual residues by surface potential difference (SPD) measurements was reported [16]. This monitoring tool led us to expand towards surface analysis and preparation during wafer to wafer bonding process.…”
Section: Results Of the Surface Charge Non-uniformity After Implement...mentioning
confidence: 99%
“…Recently, Characterizing charging non-uniformity and non-visual residues by surface potential difference (SPD) measurements was reported [16]. This monitoring tool led us to expand towards surface analysis and preparation during wafer to wafer bonding process.…”
Section: Results Of the Surface Charge Non-uniformity After Implement...mentioning
confidence: 99%
“…A two-part measurement technique is applied: First, the wafer is rotated beneath the probe in a scanning surface potential difference measurement [5]. The current into the probe is then described by Equation 1.…”
Section: Scope Of Workmentioning
confidence: 99%
“…Barrier deposition can vary in thickness from center-to-edge, variation in line heights can occur from CMP non-uniformities across wafer, via and trench profiles vary from center-to-edge due to RIE non-uniformities, and temperature variation across wafer during anneals are not uncommon -all or some of these might lead to variability in alloy segregation from center-toedge. Figure1 (a) and (b) Cartoon illustration and typical EDX/EELS signature from Mn segregating at the top of a groundrule Cu line, after anneal [5]; (c) Incomplete Mn segregation to the top due to poor-quality barrier layer [1] It is of utmost importance to know during the development stage of a technology if this variability in Mn segregation is within the tolerance limit for yielding reliable chips. This information, early in development stage, might help compensate center-to-edge variations in various process steps to keep the final alloy segregation in all chips across wafer at the required minimum.…”
Section: Introductionmentioning
confidence: 99%