Novel multi-bit SONOS type flash memory using a high-k charge trapping layer

Sugizaki, T.; Kobayashi, M.; Ishidao, M.; Minakata, H.; Yamaguchi, Masaomi; Tamura, Y.; Sugiyama, Yoshihiro; Nakanishi, Takafumi; Tanaka, Hitoshi

doi:10.1109/vlsit.2003.1221069

Cited by 72 publications

(52 citation statements)

References 3 publications

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“…Although larger trap generation resulting in early breakdown of Si + SiN stacks is always observed, it is difficult to quantify such trap generation if estimated from observed erase V FB degradation during cycling due to large hole trapping in Si + SiN stacks. It is important to note that HHG followed by I/I due to Q IET has important implications on the use of high-k materials with lower bandgap as trap layers [42]. Higher trap generation due to higher HHG (because bandgap is smaller) can lead to early breakdown of such stacks and require careful analysis.…”

Section: F Physical Mechanism Of Stack Degradation and Breakdownmentioning

confidence: 99%

Study of P/E Cycling Endurance Induced Degradation in SANOS Memories Under NAND (FN/FN) Operation

Sandhya

Oak

Chattar

et al. 2010

IEEE Trans. Electron Devices

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Abstract-Program/Erase (P/E) cycling endurance in poly-Si/Al 2 O 3 /SiN/SiO 2 /Si (SANOS) memories is systematically studied. Cycling-induced trap generation, memory window (MW) closure, and eventual stack breakdown are shown to be strongly influenced by the material composition of the silicon nitride (SiN) charge trap layer. P/E pulsewidth and amplitude, as well as starting program and erase flatband voltage (V FB ) levels (therefore the overall MW), are shown to uniquely impact stack degradation and breakdown. An electron-flux-driven anode hole generation model is proposed, and trap generation in both SiN and tunnel oxide are used to explain stack degradation and breakdown. This paper emphasizes the importance of SiN layer optimization for reliably sustaining large MW during P/E operation of SANOS memories.

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Section: F Physical Mechanism Of Stack Degradation and Breakdownmentioning

confidence: 99%

Study of P/E Cycling Endurance Induced Degradation in SANOS Memories Under NAND (FN/FN) Operation

Sandhya

Oak

Chattar

et al. 2010

IEEE Trans. Electron Devices

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“…In contrast, the height of an HfO 2 conduction barrier is only 1.5 eV with respect to the Si conduction band [15]. So, the barrier height is larger for Al 2 O 3 /Si than for HfO 2 /Si.…”

Section: Film Depositionmentioning

confidence: 87%

Improvement of charge trapping characteristics of Al2O3/Al-rich Al2O3/SiO2 stacked films by thermal annealing

et al. 2013

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Thin film Al 2 O 3 /Al-rich Al 2 O 3 /SiO 2 structures were fabricated on p-Si substrates.Radio-frequency magnetron co-sputtering was used to form Al-rich Al 2 O 3 thin film as the charge-trapping layer of nonvolatile Al 2 O 3 memory. Capacitance-voltage measurements showed a large hysteresis due to charge trapping in the Al-rich Al 2 O 3 layer. The charge trap density was estimated to be 42.7 × 10 18 cm -3 , which is the largest value ever reported for an Al-rich Al 2 O 3 layer; it is six times larger than that of a conventional metal-nitride-oxide-silicon memory. Thermal annealing was found to reduce the leakage current of the Al 2 O 3 blocking layer, thereby providing this structure with better data retention at room temperature than an as-deposited one. In addition, the annealed structure was found to exhibit good data retention even at 100°C.

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“…In Al-rich Al 2 O 3 , the localized level is thought to be about 2.4 eV from the conduction band [14]. Regarding conduction band offsets, the band diagram in Fig.…”

Section: Methodsmentioning

confidence: 99%

Charge trapping characteristics of Al2O3/Al-rich Al2O3/SiO2 stacked films fabricated by radio-frequency magnetron co-sputtering

et al. 2011

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A thin-film structure comprising Al 2 O 3 /Al-rich Al 2 O 3 /SiO 2 was fabricated on Si substrate. We used radio-frequency magnetron co-sputtering with Al metal plates set on an Al 2 O 3 target to fabricate the Al-rich Al 2 O 3 thin film, which is used as a charge storage layer for nonvolatile Al 2 O 3 memory. We investigated the charge trapping characteristics of the film. When the applied voltage between the gate and the substrate is increased, the hysteresis window of capacitance-voltage (C-V) characteristics becomes larger, which is caused by the charge trapping in the film. , which is 2.6 times larger than that of the trap memory using SiN as the charge storage layer. The device structure would be promising for lowcost nonvolatile memory.

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Novel multi-bit SONOS type flash memory using a high-k charge trapping layer

Cited by 72 publications

References 3 publications

Study of P/E Cycling Endurance Induced Degradation in SANOS Memories Under NAND (FN/FN) Operation

Study of P/E Cycling Endurance Induced Degradation in SANOS Memories Under NAND (FN/FN) Operation

Improvement of charge trapping characteristics of Al2O3/Al-rich Al2O3/SiO2 stacked films by thermal annealing

Charge trapping characteristics of Al2O3/Al-rich Al2O3/SiO2 stacked films fabricated by radio-frequency magnetron co-sputtering

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