Novel Silicon-on-Insulator Lateral Power Device with Partial Oxide Pillars in the Drift Region

Abstract

In this paper, a novel silicon-on-insulator (SOI) lateral power device with partial oxide pillars in the drift region is proposed and investigated using a three dimensional device simulator. The structure is characterized by the alternate doped silicon pillars and oxide pillars in the drift region, which can be fabricated by the dielectric isolation process without any additional mask. Owing to the modulation of the oxide pillars, a new additional electric field peak is introduced in the middle of the drift region, thus reducing the surface electric field peaks and transferring the breakdown location. Compared with the conventional reduced surface field (RESURF) device, a 21.5% increase in the breakdown voltage and a 50% increase in the figure of merit (FOM) are obtained in the novel device.

Analytical model for silicon-on-insulator lateral high-voltage devices using variation of lateral thickness technique

“…[1][2][3] One of the main issues concerning the design of the SOI device is the trade-off between breakdown voltage (BV) and specific onresistance (R sp ). [4][5][6][7] To resolve this issue, many technologies have been proposed. Reduced surface field (RESURF) technologies are commonly used to design power devices on SOI substrates for high-voltage and high-power applications.…”

Low Specific On-resistance SOI LDMOS Device with P+P-top Layer in the Drift Region

“…Actually, the deep T P and long L P means a narrow current flow channel under the P + region, leading to a large R ld2. Moreover, the figure of merit (FOM=BV 2 /R sp ) [20] is also shown in Fig. 7 to evaluate the performance of the device.…”

Novel silicon-on-insulator lateral power device with step width drift region

“…An effective approach to improve the trade-off characteristics between the BV and R on,sp is to introduce several additional electric field peaks in the drift region. The structures include step doping (SD) [5,6] , step thickness (ST) [7,8] , buried oxide step structure (BOSS) [9,10] , step buried oxide interface charges (SBIC) [11] variable low-k dielectric buried layer and a buried p-layer (VLKD) [12] , and partial oxide pillar (POP) [13] . However, more masks would be required to fabricate the step doping SOI layer, the thickness SOI layer and step buried oxide layer, the process complexity and fabrication cost would increase.…”