An organic interposer technology with ultrafine line and space is required to achieve high-density interconnection between chips. In this article, we propose a high reliability, ultrafine trench wiring process. Currently, trench wiring is made by laser ablation of dielectric, sputtering, copper plating, and then chemical mechanical polishing (CMP). However, it is challenging to achieve fine trench with smooth side wall using laser ablation, and CMP is also not suitable because of its high assembly cost. Reliability is another challenge because of the narrower and thinner insulator.
We have developed a photosensitive insulation film (PIF) with fine resolution. The trench wiring of 2/2 μm line and space has been successfully assembled by photolithography, plating, and surface planer method as the alternative to CMP. The wiring layer of 2/2 μm line and space, which is covered with a thin barrier metal layer and PIF, has passed the biased highly accelerated temperature and humidity stress test (HAST) screening.
A copper paste is applied as a seed layer instead of sputtering. The sintered copper filled with adhesive paste into the copper pores is compatible as the seed layer, and the wiring layer of 10/10 μm line and space has passed the reliability tests such as moisture sensitivity level 2 (MSL2), thermal cycling test, and biased HAST.