2021
DOI: 10.1109/ted.2021.3097979
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Numerical Study of SiC MOSFET With Integrated n-/n-Type Poly-Si/SiC Heterojunction Freewheeling Diode

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Cited by 24 publications
(10 citation statements)
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“…The Q gd is smaller than 164.6% of the PS-TMOS due to the source-connected SG and p-pillar shield region working together to reduce the overlap area between gate and drain of the GSDP-TMOS structure. Moreover, the high-frequency figure of merit (HF-FOM, R on,sp × Q gd,sp ) is a very important parameter to comprehensively evaluate the electrical performances of SiC power devices, [38][39][40] and it can be obtained by calculating the R on,sp and Q gd,sp values of the above two structures. The HF-FOM (R on,sp × Q gd,sp ) of the PS-TMOS is 271.1 mΩ•nC.…”
Section: Simulation Results and Discussionmentioning
confidence: 99%
“…The Q gd is smaller than 164.6% of the PS-TMOS due to the source-connected SG and p-pillar shield region working together to reduce the overlap area between gate and drain of the GSDP-TMOS structure. Moreover, the high-frequency figure of merit (HF-FOM, R on,sp × Q gd,sp ) is a very important parameter to comprehensively evaluate the electrical performances of SiC power devices, [38][39][40] and it can be obtained by calculating the R on,sp and Q gd,sp values of the above two structures. The HF-FOM (R on,sp × Q gd,sp ) of the PS-TMOS is 271.1 mΩ•nC.…”
Section: Simulation Results and Discussionmentioning
confidence: 99%
“…Some researchers embed heterojunction diodes in power devices to improve the electrical performance of the devices. [24][25][26][27][28][29] Yu et al [24] reported a novel SiC power MOS-FET structure. Yoon [25] proposed a SiC MOSFET insted heterojunction diode, which provided some protection against the electric field.…”
Section: Introductionmentioning
confidence: 99%
“…The barrier height for electrons Φ BN in a p-type polysilicon/n-type SiC HD [22][23][24] could be reduced to about 1.48 eV, resulting in a small V F for the device. While integrating an n-type polysilicon/n-type SiC HD 25) is also proposed to further decrease V F due to the lower Φ BN of about 0.68 eV across the n-type HD. Compared with previous approaches, the n-type polysilicon/n-type SiC HD has the lowest barrier height, resulting in a smallest cut-in voltage of ∼0.5 V, which should be considered as the best integration solution so far.…”
Section: Introductionmentioning
confidence: 99%