Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications

Seyedi, Azam; Aunet, Snorre; Kjeldsberg, Per Gunnar

doi:10.1109/norchip.2019.8906911

Cited by 7 publications

(12 citation statements)

References 27 publications

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“…In this section, we review Nwise cell characteristics [55] and describe Pwise cell characteristics. Our area-efficient Nwise and Pwise cells consist of 10 transistors and are suitable for high-density designs for space applications.…”

Section: Memory Cell Design Detailsmentioning

confidence: 99%

“…Fig. 2(a) shows the circuit structure of the Nwise cell [55]. A cross-coupled pair consisting of two NMOS transistors (N1 and N2) provides the main storage part of the cell while another cross-coupled pair of two NMOS transistors (N5 and N6) acts as the backup part.…”

Section: A Cell Schematics 1) Nwise Cell Schematicmentioning

confidence: 99%

“…When WL is asserted for the read operation, EQ and PCB are lifted and precharging of the sense amplifier FIGURE 3. The test bench circuit that consists of a one-column set that containing 64 Nwise (Pwise) cells, a precharge circuit, a write circuit, and an output sense amplifier [55], [73].…”

Section: ) Nwise Memory Cell Designmentioning

confidence: 99%

“…Authors of this paper have previously proposed the Nwise cell as the first highly reliable radiation hardened SRAM cell designed with 28nm FD-SOI [55]. Inspired from the Nwise cell, in this paper we introduce another highly reliable radiation hardened SRAM cell, the Pwise cell.…”

Section: Introductionmentioning

confidence: 99%

“…In the last part, we review recent proposed robust memory designs. In Section III Memory Cell Design Details, we review the Nwise cell [55] and introduce our new proposed Pwise cell. We explain the characteristics of both cells including schematic description, operational behavior, and analyses of SEU and MEU robustness.…”

Section: Introductionmentioning

confidence: 99%

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Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements

2022

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SRAM cells are widely used to design memory blocks of, e.g., caches, register files, and translation lookaside buffers. Depending on the SRAM application, the design requirements are different. For instance, in space applications, alongside energy efficiency, reliability is a main issue since the system is launched into space with a limited energy budget and stay exposed to high doses of radiation strikes for a long time. The Nwise cell has recently been proposed by the authors of this paper as the first highly reliable radiation hardened SRAM cell designed with 28nm FD-SOI. In this paper, inspired from the Nwise cell, we introduce another highly reliable radiation hardened SRAM cell, the Pwise cell, which is also designed with 28nm FD-SOI technology. Through comprehensive simulations of state-of-the-art cells, we show that both the Nwise and Pwise cells are competitive radiation hardened SRAMs to use in different memory blocks for space applications: (1) Both have the highest level of Single Event Upsets (SEU) tolerance capability for the temperature range deployed in space applications; further, both have the highest level of the tolerance capability to Multi Event Upsets (MEU). ( 2) Compared with the simulated cells that have comparable tolerance capability, the Nwise cell has low read delay and read power consumption, hence, it can be a good choice for space application cache designs, while the Pwise cell can be a proper candidate for space application register file designs since it has low write and read delay.

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Section: Memory Cell Design Detailsmentioning

confidence: 99%

Section: A Cell Schematics 1) Nwise Cell Schematicmentioning

confidence: 99%

Section: ) Nwise Memory Cell Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements

2022

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Radiation Effects and Their Impact on SRAM Design

Alekhya,

Nanda,

Pandey

2023

Advanced Ultra Low‐Power Semiconductor Devices

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A review on radiation‐hardened memory cells for space and terrestrial applications

Mukku¹,

Lorenzo²

2022

Circuit Theory & Apps

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Over the past four decades, single event upset (SEU) and single event multiple node upset (SEMNU) have become the major issues in the memory area.Moreover, these upsets are prone to reliability issues in space, terrestrial, military, and medical applications. This article concisely reviews different researchers and academicians who proposed resilience techniques and methods to mitigate this upset mess. In addition, we also investigated the importance of Q Crit and the impact of Q Crit on device scaling parameters in upset mechanism, probability of memory failure, and the figure of metrics for the stability of memory cells.critical charge, figure of metric, single event upset, single event multiple node upset, soft error | INTRODUCTIONTo enhance the functionality of system-on-chip (SoC), designers scale down the dimensions of the transistors. 1 According to the international technology roadmap for semiconductors (ITRS) prediction on memory size, and its processing engines on mobile type SoC, it is expected to rise by a factor of 18 between 2013 and 2025, 2,3 which is shown in Figure 1. Massive increasing the transistor count certainly increases the power consumption and degrade the mobile battery's life.Recent SoCs are embedded with static random access memory (SRAM) memories due to the faster and more reliable read/write approaches. Therefore, these SRAMs are used as cache and main memories. Moreover, SRAM memories occupy a maximum area on SoC's. 2 Hence, chip designers scale down the process technology of the memories. The problem with process technology scaling would lower the standard operating voltage, conversely, due to the process variations, memory density increases. 4 Figure 2 shows the trends of industrial standard processors and SRAM memories with various operating voltages at different technology nodes presented in ISSCC. 3 Scaling the process technology node of SRAM memories is more sensitive to transistor variations. 5 This scaling also increases the soft error rate (SER). Ibe et al 6 discuss the SER of SRAM memories in 22 nm node rises by a factor of 7 as compared with 130 nm design. On the other hand, when an electronic component is subjected to radiation, its electrical properties change due to technology node scaling, large densities, and lower operating voltages. These exposures to radiation cause temporary or permanent system breakdown.Three distinct radiation environments are feasible to define, from earth's sea level to the planet's space orbit. They are terrestrial, atmospheric, and van Allen belt radiations. The National Aeronautical Space Administration (NASA) investigated spacecraft anomalies between 1974 and 1994 space missions. 7 Among those 100 various missions, it is clear that 35% and above of anomalies are caused to spacecraft failure due to the electronic component's radiation effects. So

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Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications

Cited by 7 publications

References 27 publications

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements

Radiation Effects and Their Impact on SRAM Design

A review on radiation‐hardened memory cells for space and terrestrial applications

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