Observation of three-dimensional shell filling in cylindrical silicon nanowire single electron transistors

Abstract

The authors have measured addition energy spectra from gate-all-around twin silicon nanowire single electron transistors (SETs) with the radius of 5nm and with circular cross sections. Nonmonotonically varying addition energies are observed and the authors interpret them as shell fillings of silicon nanowire quantum dots with three-dimensional harmonic confinement potentials. A 45nm long SET shows 2-1-2-1 filling behavior while a 38nm long SET exhibits 1-2-2-1 filling. These filling behaviors match with the calculated degeneracies of nanowires with different confinement strengths.

From quantum dots to quantum wires: Electronic structure of semiconductor nanorods

“…4 Not many experimental addition spectra of short NRs can be found in the literature. Long and wide Si NWs display a uniform peak height and width and equidistant spacing in the current vs gate voltage spectrum 5 while shorter thinner Si NRs show a more irregular spectra, 6 thus revealing a shell structure.…”

“…2,6,7 Thus, two-dimensional ͑2D͒ harmonic QDs has a 2, 4, 6, 8… degeneracy pattern yielding high peaks in the addition energy spectrum at N =2,6,12,20... electrons, 8 this structure being partially destroyed by elliptical deformation of the QD. 9 On the other hand, the confining potential of a spherical colloidal nanocrystal, typically synthesized by wet chemistry methods, is better represented by a steplike hard wall potential, 10 which corresponds to the band gap difference between neighboring materials.…”

Possibility of Transport Through a Single Acceptor in a Gate-All-Around Silicon Nanowire PMOSFET

“…At low T , we usually observe regular current oscillations, which are originated from single hole tunneling of the quantum dot defined by the gate-bias-induced band bending of the p source/lightly doped nanowire/p drain [12], [14], [15] [also see the band diagram of Fig. 5(b)].…”

“…Here, we use the penetration depth (the length of the p region in the SNW) of 15 nm [12]. The total heat budget after boron ion implantation of the source and the drain region is 800 • C for t = 10 min.…”

“…Previously, we reported the characteristics of twin SNWFETs fabricated by using full CMOS processes [10]. Low-temperature (T ) characterization of these devices exhibited interesting single-electron tunneling [11] and shell filling behaviors [12]. However, so far, the effect of single dopant on these GAA structure has rarely been reported.…”