On-Orbit Upset Rate Prediction at Advanced Technology Nodes: a 28 nm FD-SOI Case Study

Malherbe, Victor; Gasiot, Gilles; Soussan, Dimitri; Autran, Jean‐Luc; Roché, Philippe

doi:10.1109/tns.2016.2634604

Cited by 17 publications

(7 citation statements)

References 12 publications

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“…Both are material dependent time constants [27]. According to [28], we set τ r = 1ps and τ f = 5ps for the considered 28nm FD-SOI technology node. The critical charge (Q crit ) is obtained by increasing Q dep until the state of a sensitive node is changed.…”

Section: Design Methodology and Simulation Resultsmentioning

confidence: 99%

Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications

Seyedi

Aunet

Kjeldsberg

2019

2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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In the electronics space industry, memory cells are one of the main concerns, especially in term of reliability, since radiation particles may hit cell nodes and disturb the state of the cell, possibly causing fatal errors. In this paper we propose the Nwise SRAM cell, an area-efficient and highly reliable radiation hardened memory cell for use in high-density memories for space applications. Simulations confirm that the proposed Nwise cell is fully tolerant to single event upsets (SEU) in any one of its nodes regardless of upset polarity. Meanwhile, compared with the RHBD-10T cell, the latest area-efficient radiation hardened memory cell, it has higher robustness: the minimum critical charge of Nwise is 4.1× 4.1× 4.1× higher than the minimum critical charge of the RHBD-10T cell. It also shows 23% and 12% improvements in read and write static noise margin (SNM). Furthermore, compared with RHBD-10T, up to 18.4% and 7.0% power savings are obtainable during write and read operations respectively. Nwise is about 2.28× × × faster than RHBD-10T during the more frequent read operation, with a similar penalty in write time. Finally, Nwise is the first proposed high density and reliable radiation hardened memory cell that has been designed using the 28nm FD-SOI technology node.

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Section: Design Methodology and Simulation Resultsmentioning

confidence: 99%

Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications

Seyedi

Aunet

Kjeldsberg

2019

2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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“…According to [41], we set τ r = 1ps and τ f = 5ps for the considered 28nm FD-SOI technology node. Fig.…”

Section: A Seu Injection Modelingmentioning

confidence: 99%

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements

2022

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SRAM cells are widely used to design memory blocks of, e.g., caches, register files, and translation lookaside buffers. Depending on the SRAM application, the design requirements are different. For instance, in space applications, alongside energy efficiency, reliability is a main issue since the system is launched into space with a limited energy budget and stay exposed to high doses of radiation strikes for a long time. The Nwise cell has recently been proposed by the authors of this paper as the first highly reliable radiation hardened SRAM cell designed with 28nm FD-SOI. In this paper, inspired from the Nwise cell, we introduce another highly reliable radiation hardened SRAM cell, the Pwise cell, which is also designed with 28nm FD-SOI technology. Through comprehensive simulations of state-of-the-art cells, we show that both the Nwise and Pwise cells are competitive radiation hardened SRAMs to use in different memory blocks for space applications: (1) Both have the highest level of Single Event Upsets (SEU) tolerance capability for the temperature range deployed in space applications; further, both have the highest level of the tolerance capability to Multi Event Upsets (MEU). ( 2) Compared with the simulated cells that have comparable tolerance capability, the Nwise cell has low read delay and read power consumption, hence, it can be a good choice for space application cache designs, while the Pwise cell can be a proper candidate for space application register file designs since it has low write and read delay.

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“…The most widely used model considers that an SET can be described by a double-exponential current pulse I inj (t) on the transistor [26][27][28][29]. The current I inj (t) is defined by Equation (2) where Q inj is the charge injection level calculated by Equation (3), K is related to the material characteristics and the radiation intensity, τ 1 is the collection time constant for a junction, and τ 2 is the ion track establishment time constant [26][27][28]:…”

Section: Set Modelmentioning

confidence: 99%

Voltage-Controlled Magnetic Anisotropy MeRAM Bit-Cell over Event Transient Effects

Maciel

Marques

Naviner

et al. 2019

JLPEA

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Magnetic tunnel junction (MTJ) with a voltage-controlled magnetic anisotropy (VCMA) effect has been introduced to achieve robust non-volatile writing control with an electric field or a switching voltage. However, continuous technology scaling down makes circuits more susceptible to temporary faults. The reliability of VCMA-MTJ-based magnetoelectric random access memory (MeRAM) can be impacted by environmental disturbances because a radiation strike on the access transistor could introduce write and read failures in 1T-1MTJ MeRAM bit-cells. In this work, Single-Event Transient (SET) effects on a VCMA-MTJ-based MeRAM in 28 nm FDSOI CMOS technology are investigated. Results show the minimum SET charge Q c required to reach the access transistor associated with the striking time that can lead to an unsuccessful switch, that is, an error in the writing process (write failure). The synchronism between the fluctuations of the magnetic field in the MTJ free layer and the moment of the write pulse is also analyzed in terms of SET robustness. Moreover, results show that the minimum Q c value can vary more than 100% depending on the magnetic state of the MTJ and the width of the access transistor. In addition, the most critical time against the SET occurrence may be before or after the write pulse depending on the magnetic state of the MTJ.

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On-Orbit Upset Rate Prediction at Advanced Technology Nodes: a 28 nm FD-SOI Case Study

Cited by 17 publications

References 12 publications

Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications

Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements

Voltage-Controlled Magnetic Anisotropy MeRAM Bit-Cell over Event Transient Effects

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