On routability prediction for field-programmable gate arrays

Chan, P.K.; Schlag, Martine D. F.; Zien, Jason Y.

doi:10.1145/157485.164915

Cited by 48 publications

(31 citation statements)

References 7 publications

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“…Chan et al [5] applied classical models [12] and [13] to predict required channel width for a fixed FPGA architecture. Rahman et al [19] used the modern wire model [9] to formulate an interconnect model predicting 2D and 3D channel width requirement.…”

Section: Related Workmentioning

confidence: 99%

Modeling routing demand for early-stage FPGA architecture development

Fang

Rose

2008

Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays

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Architecture development for FPGAs has typically been a very empirical discipline, requiring the synthesis of benchmark circuits into candidate architectures. This is difficult to do in the early stages of architecture development, however, because there is no complete architecture to synthesize circuits into. The effort required to create prototype tools for nascent architectures is far too great for every new logic block or routing architecture idea, and so it would be extremely helpful to have a simple and intuitive FPGA interconnect model to guide the architect.In this paper we present such an interconnect model for island-style FPGAs, whose single output is the estimated routing demand (often referred to as W, the number of routing tracks per channel) for an FPGA as a function of several logic block, circuit and routing architecture parameters. The goal of this model is to be as simple as possible, while still accurate enough to be useful, to provide understanding and intuition on FPGA routing. Our methodology is empirical -we propose model forms based on empirical observations, intuition and some derivation, and then fit models to experimentally generated data.We show the development of the model in stages, beginning with a fully flexible FPGA, and gradually proceeding to one which includes the key parameters that control the flexibility of FPGA routing, and one key parameter describing the logic block and another relating to the typical circuit. We then show how to use these models in early-stage architecture development to provide feedback on several aspects of logic block architecture. We also show how the model can be used to explore the routing architecture space itself and to provide an overall intuition for architecture development.

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Section: Related Workmentioning

confidence: 99%

Modeling routing demand for early-stage FPGA architecture development

Fang

Rose

2008

Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays

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“…Rent's exponent is a measure of interconnection complexity of a design, and reported values of p are in the range of 0.12 to 0.8 [49,67,68]. In Generally, memory circuits (SRAMs or DRAMs) are associated with smaller values of Rent's exponent, and logic circuits are associated with higher values of Rent's exponent [49].…”

Section: Rent's Rulementioning

confidence: 99%

System-level performance evaluation of three-dimensional integrated circuits

Rahman¹,

Reif²

2000

IEEE Trans. VLSI Syst.

176

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As the critical dimensions in VLSI design continue to shrink, system performance of integrated circuits (ICs) will be increasingly dominated by interconnect delay [1]. For the technology generations approaching 50 nm and beyond, innovative system architectures and interconnect technologies will be required to meet the projected system performance [2]. Interconnect material solutions such as copper and low-k inter-level dielectric (ILD) offer only a limited improvement in system performance. Significant and scalable solutions to the interconnect delay problem will require fundamental changes in system design, architecture, and fabrication technologies.Three-dimensional (3-D) ICs can alleviate interconnect delay problems by offering flexibility in system design, placement and routing. They (3-D ICs) can be formed by vertical integration of multiple device layers using wafer bonding, recrystallization, or selective epitaxial growth. The flexibility to place devices along the vertical dimension allows higher device density and smaller form factor in 3-D ICs. The critical signal path that may limit system performance can also be shortened to achieve faster clock speed. By 3-D integration, device layers fabricated with different front-end process technologies can be stacked along the 3 rd dimension to form systems-on-a-chip [3]. In this thesis work, opportunities and challenges for 3-D integration of logic networks, microprocessors, and programmable logic have been explored based on system-level modeling and analysis. A stochastic wire-length distribution model has been derived to predict interconnection complexity in 3-D ICs. As more device layers are integrated, the 3-D wire-length distribution becomes narrower compared to that of 2-D ICs, resulting in a significant reduction in the number and length of semi-global and global wires. In 3-D ICs with 2-4 device layers, 30% -50% reduction in wire-length can be achieved. Besides performance modeling, thermal analysis has also been performed to assess power dissipation and heat removal issues in 3-D ICs. The total capacitance associated with signal interconnects and clock networks can be reduced by 3-D integration, leading to lower power dissipation for system performance comparable to that of 2-D ICs. However, for higher system performance in 3-D ICs, power dissipation increases significantly, and it is likely that innovative cooling techniques will be needed for reliable operation of devices and interconnects.

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“…Most industrial placers of which we are aware use some variant of annealingbased semi-custom placement [6], with modifications to suit specific architectures. Interestingly, [22] recently revived for FPGAs some earlier stochastic wirability prediction techniques originally designed to evaluate how probable it was that a particular netlist could be wired in a given gate array architecture. Again, we regard this as a reaction to the continuing difficulty of ensuring that complex designs can be packed onto a specific FPGA architecture with 100% routability.…”

Section: Previous Approachesmentioning

confidence: 99%

Performance-driven simultaneous place and route for row-based FPGAs

Nag

Rutenbar

1994

Proceedings of the 31st Annual Conference on Design Automation Conference - DAC '94

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Sequential place and route tools for FPGAs are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty in predicting these at the placement level. A new performance-driven simultaneous placement / routing technique has been developed for row-based designs. Up to 28% improvements in timing and 33% in wirability have been achieved over a traditional sequential place and route system in use at Texas Instruments for several MCNC benchmark examples.

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On routability prediction for field-programmable gate arrays

Cited by 48 publications

References 7 publications

Modeling routing demand for early-stage FPGA architecture development

Modeling routing demand for early-stage FPGA architecture development

System-level performance evaluation of three-dimensional integrated circuits

Performance-driven simultaneous place and route for row-based FPGAs

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