On the kinetics of platinum silicide formation

Abstract

In this work, the kinetics of platinum silicide formation for thin Pt films (50 nm) on monocrystalline ⟨100⟩ silicon is investigated via in situ resistance measurements under isothermal (197–275 °C) conditions. For Pt2Si diffusion limited growth was observed. For PtSi formation, however, no linear relation between silicide thickness and √t was found. PtSi growth over time could be described using the Avrami relation rendering Avrami exponent n=1.4±0.1. Additionally, an effective activation energy EA=1.7±0.1 eV was derived using the Avrami k values. The findings are important for obtaining well defined silicide films and silicide-to-silicon contacts.

Subsurface analysis of semiconductor structures with helium ion microscopy

“…Annealing this structure to a temperature of 350°C allows the Pd to diffuse into the Si to form a Pd 2 Si alloy. Similar to Pt, Pd can not diffuse into SiO 2 but only in Si [15]. As a result, the Pd diffuses exclusively in between the top and bottom siliconoxide barriers, converting the sandwiched silicon layer into the intermetallic Pd 2 Si phase.…”

The Materials Science Foundation Supporting the Microfabrication of Reliable Polyimide–Metal Neuroelectronic Interfaces

“…It is unlikely that the oxygen originated from the upper a-SiC:H surface, as no detectable oxygen diffusion through a-SiC:H was identified for metal stacks A-C. Annealing thin-film platinum deposited directly onto Si wafers results in diffusion-limited platinum-silicide formation that starts at ≈200 °C and progresses from Pt 3 Si→Pt 2 Si→PtSi. [75,76] While direct comparisons cannot be made between films formed using Si wafers or a-SiC:H as the source of silicon, it is apparent that annealing films to 450 °C causes a complete depletion of the platinum film in favor of silicide formation and cannot be avoided unless a diffusion barrier such as titanium is used.…”

Planar Junctionless Field-Effect Transistor for Detecting Biomolecular Interactions

“…For example, ohmic contact with the lightly doped thin device layer is best achieved by the formation of a thin layer of PtSi alloys at the interface of Ta/Pt and silicon. However, this process is too sensitive to the thickness of the silicide formation and the annealing temperature to provide reproducible results with our device layer thickness [ 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 ]. We have overcome this issue by optimization of the annealing process to get a reliable planar junctionless FET device, and in the end, we have demonstrated the pH sensing performance of our fabricated device.…”