On the optimization of MOS circuits

Abstract

Optimizing the number of transistors in a complex MOS gate is significant for minimizing chip area and delay in VLSI designs. Unfortunately, such optimization process is an NP-C problem. The worst case computational complexity of graphoriented algorithms used in existing approaches is exponential in the number of transistors. In this paper, we address this problem through the use of bridging switches. We propose a theory and an algorithm for optimization of MOS switch networks using an edge-merging technique. The worst case computational complexity of the heuristic algorithm proposed is O(n5e2), where n is the number of nodes and e is the number of edges in the switch network.

Transistor-Level Synthesis for Low-Power Applications

“…To provide a comparison measure, we report here results obtained for the four functions F 4 , F 5 , F 6 and F 13 proposed in [3] and used also in [3,28,8]. Table 1 contains the [3], Columns 4 and 5 give the T count and corresponding S cost for the diagrams obtained in [8], and Columns 6 and 7 give the T count and corresponding S cost for the diagrams obtained by the proposed approach.…”

“…The examination order of the product terms affects the final solution (the problem is NP-hard [28]). Heuristic measures can be applied, such as examining the terms in descending (or ascending) order of the sum of the switching activities of their literals, or examining next the product term that has maximum intersection (in terms of literals with switching activities above some bound) with the already placed product terms, or simply examining the product terms in some random ordering.…”

“…That is, the power minimization is implicit in these methodologies. Two main approaches exist: factorization methods [5,1,2,3,18] and graph-oriented methods [6,27,10,28,13,23,8]. All these methodologies try to minimize the total number of transistors but they do not take into account that certain inputs are more critical (i.e., have higher switching activity) than others.…”

A graph-based technique to optimize transistor networks

“…An interesting detail is that the proposed approach may derive bridge networks like methods proposed by [5] and [6]. The example illustrated in Figure 8 presents a bridge configuration (through edge 'E').…”

“…They are based on graph optimizations, were each edge in the graph keeps an association with a transistor in the network. The main idea is try to minimize the edges in an existent graph [5] or to compose a new graph with a reduced number of edges [6].…”