On the topology and number of operating points of MOSFET circuits

Goldgeisser, L.B.; Green, M.M.

doi:10.1109/81.904887

Cited by 9 publications

(4 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A different, geometric approach stems from the work of Brayton and Moser [45,46]; later results in this direction can be found in [47][48][49][50][51][52][53]. Other developments in the last two decades have concerned singularities in DAE models [10,11,29,30,33], general circuit modelling [14, 15, 17-19, 31, 39, 52-56], and qualitative results for certain circuit families [27,28,57,58], besides of course numerical aspects.…”

Section: Qualitative Results Based On State-space Modelsmentioning

confidence: 98%

Qualitative features of matrix pencils and DAEs arising in circuit dynamics

Riaza

Tischendorf

2007

Dynamical Systems

View full text Add to dashboard Cite

The dynamical behaviour of nonlinear electrical circuits is usually modelled in the time domain by differential-algebraic equations (DAEs). The differentialalgebraic formalism drives qualitative analyses based on linearization to a matrix pencil setting. In this context, the present paper performs a spectral analysis of matrix pencils and DAEs arising in nonlinear circuit theory. Specifically, the non-singularity, hyperbolicity and asymptotic stability of equilibria are addressed in terms of circuit topology. The differential-algebraic framework puts the results beyond those already known for state-space models, unfeasible in many actual problems. The topological conditions arising in this qualitative study are proved independent of those supporting the index, and therefore they apply to both index-1 and index-2 configurations. The approach illustrates how graph theory, matrix analysis and DAE theory interact in the dynamical study of nonlinear circuits.

show abstract

Section: Qualitative Results Based On State-space Modelsmentioning

confidence: 98%

Qualitative features of matrix pencils and DAEs arising in circuit dynamics

Riaza

Tischendorf

2007

Dynamical Systems

View full text Add to dashboard Cite

show abstract

“…A feedback structure is identified by setting all independent source values to zero, by open-circuiting and/or short-circuiting resistors, and by replacing all but two of the transistors by a pair of open and/or short circuits. The extension of the topological criteria to more general three-terminal devices (including FETs) [67], circuits employing Ebers-Moll-modeled transistors having variable current-gains [18], and metal-oxide-semiconductor field-effect transistor (MOSFET) circuits [15] have been also established.…”

Section: Number Of DC Operating Pointsmentioning

confidence: 99%

DC operating points of transistor circuits

Trajković

2012

NOLTA

View full text Add to dashboard Cite

Abstract:Finding a circuit's dc operating points is an essential step in its design and involves solving systems of nonlinear algebraic equations. Of particular research and practical interests are dc analysis and simulation of electronic circuits consisting of bipolar junction and fieldeffect transistors (BJTs and FETs), which are building blocks of modern electronic circuits. In this paper, we survey main theoretical results related to dc operating points of transistor circuits and discuss numerical methods for their calculation.

show abstract

“…In [10], it was shown that the simple nMOS latch circuit shown in Fig. 1 can be made to possess five operating points, three of which are stable.…”

Section: Theoretical Backgroundmentioning

confidence: 99%

Design of CMOS Ternary Latches

Shou¹,

Kalantari²,

Green

2006

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

Abstract-This paper describes the design methodology of latches with three stable operating points. Open-loop analysis is used to obtain insight into how a conventional binary latch structure can be modified to yield a ternary latch. Four novel ternary latch structures, compatible with a standard CMOS process, are presented. Properties of each latch, including robustness of the ternary behavior, speed, and power dissipation, are described. Measurement results of four RS ternary flip-flops based on the proposed latch structures, fabricated in a standard 0.18-m CMOS process, are presented. Maximum operating frequency and skew tolerance are reported for each of the four latches.Index Terms-CMOS digital integrated circuits, CMOS memory circuits, digital integrated circuits, integrated logic circuits, multivalued logic circuits.

show abstract

On the topology and number of operating points of MOSFET circuits

Cited by 9 publications

References 6 publications

Qualitative features of matrix pencils and DAEs arising in circuit dynamics

Qualitative features of matrix pencils and DAEs arising in circuit dynamics

DC operating points of transistor circuits

Design of CMOS Ternary Latches

Contact Info

Product

Resources

About