On thermal effects in deep sub-micron VLSI interconnects

Abstract

This paper presents a comprehensive analysis of the thermal effh in advanced high performance interconnect systems arising due to selfheating under various circuit conditions, including electrostatic discharge. Technology (Cu, low-k etc) and scaling effects on the thermal characteristics of the interconnects, and on their electromigration reliability has been analyzed simultaneously, which will have important implications for providing robust and aggressive deep sub-micron interconnect design guidelines. Furthermore, the impact of these thermal effects on the design (driver sizing) and optimization of the interconnect length between repeaters at the upperlevel signal lines are investigated.

A power-optimal repeater insertion methodology for global interconnects in nanometer designs

“…In general, the repeaters are optimally sized and separated to minimize the interconnect delay. However, since these optimally sized repeaters are quite large ( 450 times the minimum sized inverter available in the relevant technology for global-tier lines [8]) and also dissipate a significant amount of power, the total power dissipation by such repeaters in large high-performance designs can be prohibitively high. However, as shown in Fig.…”

A Thermal Simulation Process Based on Electrical Modeling for Complex Interconnect, Packaging, and 3DI Structures

“…where is the electrical displacement flux, is the material permittivity, and is the charge density. The similarity between (2) and (6) shows that the thermal conductance is analogous to the electrical capacitance. But it requires that the majority electric field is within bonding dielectrics if we take advantage of corresponding capacitance problems.…”

Effects of non-uniform substrate temperature on the clock signal integrity in high performance designs

“…The volumetric heat generation in the interconnect is computed by determining the rate of power generation due to the RMS current and the rate of heat loss due to the heat transfer between the interconnect and the substrate through the insulator. As a result, the heat flow equation (1) in an interconnect can be restated as follows [6]: (2) where λ and θ are constants given as follows:…”

“…Management of thermally related issues is rapidly becoming one of the most challenging efforts in high performance chip design. At the circuit level, thermal problems have important implications for performance and reliability [1]. Furthermore, it has been recently reported that significant temperature gradients on the silicon substrate can occur due to different activity and/or different sleep modes of various functional blocks in highperformance microprocessor chips [2].…”