Operational Voltage Reduction of Flash Memory Using High-$\kappa$ Composite Tunnel Barriers

Verma, S.; Pop, Eric; Kapur, Pawan; Parat, Krishna; Saraswat, Krishna C.

doi:10.1109/led.2007.915376

Cited by 15 publications

(9 citation statements)

References 7 publications

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“…To enable scaling, the SiO 2 tunnel layer is often replaced by a composite multilayered stack [12]- [18]. The engineering of the tunnel dielectric with crested [13], VARIOT [14], symmetric composite [15] tunnel barrier, and double quantum-barrier structure [16] was also found to improve performance. However, the use of thin multilayer deposited tunnel dielectric may compromise the overall cell reliability, particularly for multilevel cell (MLC) operation which requires high P/E voltages for large MW, resulting in degraded P/E cycling endurance capability.…”

Section: Introductionmentioning

confidence: 99%

Impact of SiN Composition Variation on SANOS Memory Performance and Reliability Under nand (FN/FN) Operation

Sandhya

Oak

Chattar

et al. 2009

IEEE Trans. Electron Devices

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Abstract-Despite significant advances in structure and material optimization, poor erase (E) speeds and high retention charge loss remain the challenging issues for charge trap Flash (CTF) memories. In this paper, the dependence of SANOS memory performance and reliability on the composition of silicon nitride (SiN) layer is extensively studied. The effect of varying the Si:N ratio on program (P)/E and retention characteristics is investigated. SiN composition is shown to significantly alter the electron and hole trap properties. Varying the SiN composition from N-rich (N + ) to Si-rich (Si + ) lowers electron trap depth but increases hole trap depth, causing lower P state saturation but significant overerase, resulting in an enhanced memory window. During retention, P state charge loss depends on thermal emission followed by the tunneling out of electrons mostly through tunnel dielectric, which becomes worse for Si + SiN. Erase state charge loss mainly depends on hole redistribution under the influence of internal electric fields, which improves with Si + SiN. This paper identifies several important performances versus reliability tradeoffs to be considered during the optimization of SiN layer composition. It also explores the option for CTF optimization through the engineering of SiN stoichiometry for multilevel cell NAND Flash applications.Index Terms-Charge trap Flash (CTF), program/erase (P/E) window, retention, SANOS, silicon nitride (SiN), SONOS.

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Section: Introductionmentioning

confidence: 99%

Impact of SiN Composition Variation on SANOS Memory Performance and Reliability Under nand (FN/FN) Operation

Sandhya

Oak

Chattar

et al. 2009

IEEE Trans. Electron Devices

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“…The working principle of BGE barriers relies on the field-induced modulation of the potential barrier, which ideally should be thin and low during PIE operations, and thick and high in retention conditions, thus inducing high PIE currents and very low charge loss in retention, respectively. BGE barriers are implemented by high-K stacks according to two approaches proposed in the literature: i) crested barriers [15]; ii) VARIable Oxide Thickness (VARIOT) barriers [16,17].…”

Section: H Igh-k Band-gap Engineered Barriersmentioning

confidence: 99%

“…Unfortunately, their implementation is not straightforward in CMOS process, as abrupt Silhigh-K interfaces cannot be realized because of the formation of a thin sub-stoichiometric SiOx layer with a high defect density [18], which prevents their real feasibility [5]. This technology issue is not present in VARIOT barriers [16,17], whose operating principle is based on the electric field redistribution in the high K stack according to the Gauss's law. The strong dependence of the tunneling current on the applied voltage [16,17,19,20] arises from the combined effect of the higher field in the Si02 layer and the lower band-gap of high-K materials.…”

Section: H Igh-k Band-gap Engineered Barriersmentioning

confidence: 99%

“…This technology issue is not present in VARIOT barriers [16,17], whose operating principle is based on the electric field redistribution in the high K stack according to the Gauss's law. The strong dependence of the tunneling current on the applied voltage [16,17,19,20] arises from the combined effect of the higher field in the Si02 layer and the lower band-gap of high-K materials. [14].…”

Section: H Igh-k Band-gap Engineered Barriersmentioning

confidence: 99%

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Fundamental reliability issues of advanced charge-trapping Flash memory devices

Larcher

Padovani

2010

2010 17th IEEE International Conference on Electronics, Circuits and Systems

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The basic reliability issues of Charge Trapping (CT) Flash memory devices will be discussed from a physical perspective, highlighting the reliability implications of process and technology innovations introduced to sustain the uninterrupted device scaling down. We will focus on the reliability issues related to the charge localization inside the trapping layer and the high-K band-gap engineered stacks introduced to implement both tunnel and blocking dielectrics.We will describe the physical mechanisms responsible of reliability degradation (data retention, array disturbs, endurance), discussing briefly the issues related to ultra-scaled and vertically stacked 3D Flash memory devices.

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“…Reduction of the thickness of the tunnel oxide may solve this challenge, but it also presents a severe bottleneck due to stress-induced leakage current (SILC). Many reports document the tunnel oxide should not reduce beyond 7-8nm because of the tradeoff between P/E process and retention reliability [3][4]. This condition will restrict the betterment of the device performance in terms P/E voltage and time.…”

Section: Introductionmentioning

confidence: 99%

Optimization of high-k composite dielectric materials of variable oxide thickness tunnel barrier for nonvolatile memory

A.Hamid

Hamzah

Alias

et al. 2019

IJEECS

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Downscaling the tunnel oxide thickness has become one of the innovative solutions to minimize the operational voltage with better the programming/erasing (P/E) operation time. However, the downscaling technique faces several challenges where the conventional SiO2 tunnel layer has reached its limit. But a practical alternative has been introduced; Variable Oxide Thickness (VARIOT) technology in flash memory has been promising. VARIOT is one of tunnel barrier engineering technology for incorporating the high-k dielectric materials as a composite tunnel barrier. This paper presents the VARIOT concept to determine the optimum set of combination, the equivalent oxide thickness (EOT) and the low-k oxide thickness (Tox) for alternate high-k materials. Fowler-Nordheim (F-N) tunneling coefficients are also extracted for various combinations of VARIOT, where in this work ZrO2, HfO2, Al2O3, La2O3, and Y2O3 are used. The VARIOT optimization is conducted using 3-Dimensional (3D) Silicon Nanowire Field-Effect-Transistor (SiNWFET) device structure and simulated in TCAD Simulation tools. From the simulation results, it has found out that the high-k materials of La2O3 asymmetric stack is the excellent dielectric material among four (4) other dielectric materials; ZrO2, HfO2, Al2O3 and Y2O3 for EOT=4nm and Tox=1nm.

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Operational Voltage Reduction of Flash Memory Using High-$\kappa$ Composite Tunnel Barriers

Cited by 15 publications

References 7 publications

Impact of SiN Composition Variation on SANOS Memory Performance and Reliability Under nand (FN/FN) Operation

Impact of SiN Composition Variation on SANOS Memory Performance and Reliability Under nand (FN/FN) Operation

Fundamental reliability issues of advanced charge-trapping Flash memory devices

Optimization of high-k composite dielectric materials of variable oxide thickness tunnel barrier for nonvolatile memory

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