Optimal design of new cascade multilevel converter topology based on series connection of extended sub‐multilevel units

Summary A new basic unit of 25‐level asymmetric multilevel inverter topology is proposed in this article. The extended and cascaded topologies are developed to increase the output voltage level. Furthermore, to determine the magnitude of DC source values in each unit, two algorithms are presented. The proposed extended and cascaded structures are compared with other recent and conventional multilevel inverter topologies in terms of a number of DC sources, blocking voltage on the switches and cost of the inverter. The performance of the proposed topology is validated through the MATLAB/Simulink tool and laboratory setup for 25‐level output. The dynamic performances of proposed topology is confirmed with different loading conditions and their results are presented.

Section: Simulation and Experimental Resultsmentioning

confidence: 99%

Section: Simulation and Experimental Resultsmentioning

confidence: 99%

Section: Comparative Studymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A novel cross-connected multilevel inverter topology for higher number of voltage levels with reduced switch count

Prem¹,

Sugavanam

Abubakar³

et al. 2020

A new and generalized structure of single‐phase and three‐phase cascaded multilevel inverter with reduced power components

Mahato

Majumdar

Jana

2019

Summary The proposed work shows a novel multilevel inverter (MLI) configuration to generate a large number of voltage levels with lesser number of power switches. The proposed generalized inverter comprises basic cells cascaded to each other. Each cell of the proposed inverter can generate three‐level AC voltage using the power switches of the same rating. Both single‐phase and three‐phase MLI configurations are possible for the proposed structure. To validate the performance of the proposed MLI configuration, a nine‐level inverter using six power switches and a 27‐level inverter using nine power switches are designed and simulated in the MATLAB/Simulink environment. An experimental prototype is developed in the laboratory, and the experimental results are presented to verify the simulated results. Further, to validate the effectiveness of the proposed multilevel inverter, a comparison of the proposed MLI with recently proposed multilevel inverter has been incorporated in a detailed manner.

An improved asymmetrical multilevel inverter topology with reduced semiconductor device count

Sarwer

Siddique

Iqbal

et al. 2020

Background Multilevel Inverters have become a viable alternative to two‐level inverters because of their superior power quality, however, the increase in number of switches with their corresponding voltage stress, and dc voltage sources are the major factors for higher number of levels. Aim This paper proposes a modified and improved asymmetrical multilevel inverter with 15 output voltage levels. Materials and Methods The distinguishing feature of the proposed topology is the reduced number of switches as compared to recently introduced topologies having the same number of levels. As the number of devices has a direct relation to the cost of the inverter, therefore, reducing the devices will decrease the cost and makes the system more reliable for use in potential applications. The three different extensions of the proposed circuit is also discussed in the paper. Nearest level control technique is used as a modulation strategy to control the output voltage of the proposed topology. Results and Discussion The proposed Multilevel Inverter (MLI) has been simulated in MATLAB/SIMULINK environment. The THD analysis is also shown in the paper. Experimental results have been presented and discussed to validate the obtained simulation results. Power Loss analysis of the converter is also provided. It is done with the help of PLECS software. Conclusion The presented topology have lesser value of total standing voltage (TSV) and at the same time, there is no requirement of an H‐bridge in the structure to achieve polarity reversal for the desired levels.