Optimization of LDMOS-SCR Device For ESD Protection Based On 0.5 μm CMOS Process

Jin, Xiangliang; Wang, Yang; Zhong, Zeyu

doi:10.1109/emccompo.2019.8919854

Cited by 3 publications

(2 citation statements)

References 3 publications

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“…Firstly, the holding voltage can be increased by directly lengthening the dimension between the anode and the cathode of the device, that is, lengthening the ESD current path. Wang et al [25] designed a lateral double diffused MOSFET silicon controlled rectifier (LDMOS-SCR) for the ESD protection of single-photon detectors. By extending the distance between the anode and the cathode, the holding voltage can be raised from 3.43V to 7.72V due to the increased on-resistance.…”

Section: Introductionmentioning

confidence: 99%

Analysis of current aggregation in gate-control dual direction silicon controlled rectifier

Zhong

Wang

Jin

et al. 2021

IEICE Electron. Express

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The current aggregation mechanism created by the gate structure is proposed for electrostatic discharging (ESD). Through device simulation, the size-expanded gate structure in gate-control dual-direction silicon controlled rectifier (GC-DDSCR) is found to aggregate the surface parasitic current path and the main SCR current path. The SCR current path is consequently twisted and extended to increase the holding voltage (Vh). Two GC-DDSCRs are fabricated in a 0.5μm CMOS technology and tested by transmission line pulse (TLP). The Vh increases from 13.84V to 16.44V as the gate size expands from 2.5μm to 4.5μm. The mechanism of current aggregation is verified.

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Section: Introductionmentioning

confidence: 99%

Analysis of current aggregation in gate-control dual direction silicon controlled rectifier

Zhong

Wang

Jin

et al. 2021

IEICE Electron. Express

Self Cite

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“…Furthermore, LDMOS devices may act as HV devices and ESD protection device simultaneously. To reduce the effects of ESD, improving the self-protection performance of HV devices is significant [17][18][19][20][21][22][23][24][25][26][27][28]. Therefore, to achieve good ESD capability in devices, parameters including trigger voltage (V t1 ), holding voltage (V h ), and secondary breakdown current (I t2 ) are critical.…”

Section: Introductionmentioning

confidence: 99%

Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

et al. 2020

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An electrostatic discharge (ESD) event can negatively affect the reliability of integrated circuits. Therefore, improving on ESD immunity in high-voltage (HV) n-channel (n) lateral diffused metal–oxide–semiconductor field-effect transistor (HV nLDMOS) components through drain-side layout engineering was studied. This involved adjusting the operating voltage, improving the non-uniform turned-on phenomenon, and examining the effects of embedded-device structures on ESD. All proposed architectures for improving ESD immunity in this work were measured and evaluated using a transmission-line pulse system. The corresponding trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown current (It2) results of the tested devices were obtained. This paper first addresses the drift-region length modulation to design different operating voltages, which decreased as the drift region length and shallow trench isolation (STI) length shrunk. When an HV nLDMOS device decreased to the shortest drift region length, the Vt1 and Vh values were closest to 21.85, and 9.27 V, respectively. The It2 value of a low-voltage operated device could be increased to a maximum value of 3.25 A. For the channel width modulation, increasing the layout finger number of an HV LDMOS device did not really help the ESD immunity that because it may suffer the problem of non-uniform turned-on phenomenon. Therefore, adjusting the optimized channel width was the best one method of improvement. Furthermore, to improve the low ESD reliability problem of nLDMOS devices, two structures were used to improve the ESD capability. The first was a drain side—embedded silicon-controlled rectifier (SCR). Here, the SCR PNP-arranged type in the drain side had the best ESD capability because the SCR path was short and had been prior to triggering; however, it also has a latch-up risk and low Vh characteristic. By removing the entire heavily doped drain-side N+ region, the equivalent series resistance in the drain region was increased, so that the It2 performance could be increased from 2.29 A to 3.98 A in the structure of a fully embedded drain-side Schottky diode. This component still has sufficiently high Vh behaviour. Therefore, embedding a full Schottky-diode into an HV nLDMOS in the drain side was the best method and was efficient for improving the ESD/Latch-up abilities of the device. The figure of merit (FOM) of ESD, Latch-up, and cell area considerations improved to approximately 80.86%.

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An Improved LVTSCR Device with an Embedded BJT for ESD Protection

Fan

Zhu

Zhang

et al. 2021

2021 IEEE 30th International Symposium on Industrial Electronics (ISIE)

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Optimization of LDMOS-SCR Device For ESD Protection Based On 0.5 μm CMOS Process

Cited by 3 publications

References 3 publications

Analysis of current aggregation in gate-control dual direction silicon controlled rectifier

Analysis of current aggregation in gate-control dual direction silicon controlled rectifier

Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

An Improved LVTSCR Device with an Embedded BJT for ESD Protection

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