Optimizing Schottky S/D offset for 25-nm dual-gate CMOS performance

Connelly, Daniel; Faulkner, C.; Grupp, D. E.

doi:10.1109/led.2003.813363

Cited by 44 publications

(21 citation statements)

References 10 publications

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“…The lower capacitance value for the SB MOSFETs is linked to the presence of the SB as aforementioned, to the quantum effects, and also to the greatly reduced overlap capacitances, as discussed in [11].…”

Section: Resultsmentioning

confidence: 96%

“…Doped source-drain devices require that the gate overlaps the source and drain extensions in order to confine carriers close to the channel, preventing current flow in low-doped higher resistivity regions and reducing current drive [10]. In contrast, optimum performance in SB MOSFETs is obtained with gate "underlap," which results in lower capacitance [11]. In addition, quantum effects in the inversion layer of modern thin-oxide devices have been shown to lower the gate capacitance, particularly when the substrate is low doped as in the present SB MOSFET [12].…”

Section: Resultsmentioning

confidence: 99%

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High-Frequency Performance of Schottky Source/Drain Silicon pMOS Devices

Raskin

Pearman

Pailloncy

et al. 2008

IEEE Electron Device Lett.

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Abstract-A radio-frequency performance of 85-nm gate-length p-type Schottky barrier (SB) with PtSi source/drain materials is investigated. The impact of silicidation annealing temperature on the high-frequency behavior of SB MOSFETs is analyzed using an extrinsic small-signal equivalent circuit. It is demonstrated that the current drive and the gate transconductance strongly depend on the silicidation anneal temperature, whereas the unity-gain cutoff frequency of the measured devices remains nearly unchanged.Index Terms-Electrostatic measurement, microwave measurements, SB metal/source MOSFETs, scattering parameter measurement, Schottky barriers (SBs), semiconductor devices.

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Section: Resultsmentioning

confidence: 96%

Section: Resultsmentioning

confidence: 99%

High-Frequency Performance of Schottky Source/Drain Silicon pMOS Devices

Raskin

Pearman

Pailloncy

et al. 2008

IEEE Electron Device Lett.

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“…Therefore, other alternatives are required to further improve the performance of SB-MOSFETs. Different studies [7][8] demonstrate that the source and drain regions in SB-MOSFETs must be separated an underlap length, L un , from the gate contact, contrary to the overlap length inherent to conventional MOSFETS. Therefore, this is a key quantity in the SB-MOSFET topology, and its optimization represents a potential way of improving the overall device performance.…”

Section: Introductionmentioning

confidence: 99%

Influence of the underlap length on the RF noise performance of a Schottky Barrier MOSFET

Pascual

Rengel

Martı́n

2011

2011 21st International Conference on Noise and Fluctuations

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This paper is focused on the analysis of the highfrequency dynamic and noise performance and the static characteristics of n-type Schottky barrier (SB) MOSFETs on SOI substrate. A 2D Ensemble Monte Carlo (EMC) simulator including tunnelling transport at the Schottky interfaces has been used. Quantum transmission coefficients and treatment of image charge effects on the Schottky barrier have been carefully considered. The influence of the underlap length on the main figures of merit is described, thus showing the importance of this architecture parameter for the optimization of these devices.

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“…Since the gate has poor control over this part of the channel an underlap will result in an increased potential barrier at the gate edges. In SB devices the underlap can cause a larger performance degradation than for doped SID devices since the barrier width increases as the coupling to the gate is decreased [9].…”

Section: Introductionmentioning

confidence: 99%

Towards Schottky-barrier source/drain MOSFETs

Östling¹,

Gudmundsson²,

Hellström³

et al. 2008

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

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Section 3. Section 4 discusses device performance and noise behavior. This paper provides an overview of metal source/drain (SID) Schottky-barrier (SB) MOSFET technology. The technology offers several benefits for scaling CMOS, Le., extremely low source/drain resistance, sharp junctions from SID to channel and low temperature processing. A successful implementation of the technology needs to overcome new obstacles such as SB height engineering and precise control of silicide growth. Device design factors such as SID to gate underlap, Si film thickness and oxide thickness affect device performance owing to their effects on the SB width. In the past two years several groups have demonstrated high-performance SB MOSFETs, which places the technology as a promising candidate for future generations of CMOS technology.

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Optimizing Schottky S/D offset for 25-nm dual-gate CMOS performance

Cited by 44 publications

References 10 publications

High-Frequency Performance of Schottky Source/Drain Silicon pMOS Devices

High-Frequency Performance of Schottky Source/Drain Silicon pMOS Devices

Influence of the underlap length on the RF noise performance of a Schottky Barrier MOSFET

Towards Schottky-barrier source/drain MOSFETs

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