Proceedings of 1994 IEEE Microwave and Millimeter-Wave Monolithic Circuits Symposium
DOI: 10.1109/mcs.1994.332128
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Optimum design of distributed power-FET amplifiers. Application to a 2-18 GHz MMIC module exhibiting improved power performances

Abstract: A suitable and effective design method of distributed power amplifiers, based on the optimum FET load requirement for power operation, is proposed in this paper.An analytical determination of the gate and drain line characteristic admittances provides both the initial values and right directions for an optimum design. The best trade-offs between wide band and high power operation have been investigated.To validate the method, a FET amplifier demonstrator with a gate periphery of 1.2 mm has been manufactured at… Show more

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Cited by 19 publications
(7 citation statements)
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“…By designing the capacitances C bi carefully, the loss of the input line is compensated and the input drive at each gain cell is equalized [10].…”
Section: Circuit Designmentioning
confidence: 99%
“…By designing the capacitances C bi carefully, the loss of the input line is compensated and the input drive at each gain cell is equalized [10].…”
Section: Circuit Designmentioning
confidence: 99%
“…Of greater importance for efficiency is the ratio of the ac currents of the two devices. This ratio is independent of device sizing and is frequency-dependent, given by (6) At low frequencies, transistor provides the entire ac output current. Thus, a Darlington amplifier designed for the same power level as the common-source power amplifier must have or , the same periphery as the device in the common-source case.…”
Section: Circuit Designmentioning
confidence: 99%
“…Reported monolithic distributed power amplifiers typically have 10% to 15% PAE [3], [4]. Distributed amplifiers using tapered impedance drain-lines can in theory provide efficiencies up to the class-A limit of 50%, by eliminating the reverse termination [5], [6]. Tapered drain-line TWAs require high impedance transmission lines with limited current carrying capability, and thus are hard to realize for high output powers in monolithic form.…”
Section: Introductionmentioning
confidence: 99%
“…[26][27][28] When designers started using the various lengths of TLs between DA sections, a need for an effective method of determining their optimal lengths arose. 29 Increased requirements for the dynamic characteristics of DAs, in particular, output power and poweradded efficiency, led to non-uniform DAs and, as a result, the techniques for determining optimal load impedances and transistor peripheries for each section of DA. 30 From the view of expanding the DA operation frequency range, the cascode sections (connection of common source and common gate transistors) are considered promising.…”
Section: Introductionmentioning
confidence: 99%