PAM4 signaling considerations for high-speed serial links

Dikhaminjia, Nana; He, Jiayi; Tsiklauri, Mikheil; Drewniak, James L.; Fan, Jun; Chada, Arun; Mutnury, Bhyrav; Achkir, Brice

doi:10.1109/isemc.2016.7571771

Cited by 13 publications

(4 citation statements)

References 5 publications

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“…With the rapid evolution of global Internet, cloud computing, and 5G communication technologies, network traffic has experienced exponential growth, resulting the I/O channel capacity insufficient to meet the even-increasing demand [1,2]. To satisfy the stringent bandwidth requirement while improving the spectral efficiency, IEEE 802.3bs recommends PAM4 signaling to fulfill 200/400 Gb/s Ethernet by employing 4×50 Gb/s and 8×50 Gb/s multi-channel links [3,4]. The PAM4 signaling encodes the most significant bit (MSB) and the least significant bit (LSB), into one single symbol, thus enhancing the spectral efficiency and mitigating the bandwidth limitation for both channel and front-end circuit [5,6].…”

Section: Introductionmentioning

confidence: 99%

A 50Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation

Lv,

Xie,

Qin

et al. 2024

IEICE Electron. Express

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Aiming at the jitter issue in four-level pulse amplitude modulation (PAM4) receive link, the key causes related to the non-ideal effects of channel and data decision were analyzed, and a modified PAM4 receiver architecture was proposed. An analog equalizer with extra mid-frequency compensation and 1-tap decision-feedback equalizer were incorporated to minimize the inter-symbol interference. To alleviate the timing constraints in DFE, the feedback loop of slicer was optimized. The post-simulation results based on TSMC 28 nm CMOS process indicate that the proposed 50 Gb/s PAM4 receiver functions well over a channel with 12 dB loss at Nyquist frequency. The peak-to-peak jitters of two restored NRZ signals are 1.5 ps and 2.5 ps, respectively.

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Section: Introductionmentioning

confidence: 99%

A 50Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation

Lv,

Xie,

Qin

et al. 2024

IEICE Electron. Express

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“…Higher data rates require more precise tap coefficients for usually used equalization algorithms such as FFE and DFE. This is more crucial for 4-level pulse amplitude modulation (PAM4) signal that brings in new challenges due to inherent jitter and three slicers, [6][7][8][9]. Multi-level signal represents innovative alternative approach to increase data rates and is expected to be frequently used in future in the devices.…”

Section: Introductionmentioning

confidence: 99%

“…Multi-level signal represents innovative alternative approach to increase data rates and is expected to be frequently used in future in the devices. While multi-level signals significantly increase data rate without improving component material, nonlinear effects and other factors of signal distortion pose more challenges for several levels, therefore tap coefficients of equalizers have more effect on signal restoration, see [10][11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

Analytical method for joint optimization of FFE and DFE equalizations for multi-level signals

Dikhaminjia

Tsiklauri

Kiguradze

et al. 2022

Journal of Electrical Engineering

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Channel equalization is the efficient method for recovering distorted signal and correspondingly reducing bit error rate (BER). Different type of equalizations, like feed forward equalization (FFE) and decision feedback equalization (DFE) are canceling channel effect and recovering channel response. Separate optimization of tap coefficients for FFE and DFE does not give optimal result. In this case FFE and DFE tap coefficients are found separately and they are not collaborating. Therefore, the final equalization result is not global optimal. In the present paper new analytical method for finding best tap coefficients for FFE and DFE joint equalization is introduced. The proposed method can be used for both NRZ and PAM4 signals. The idea of the methodology is to combine FFE and DFE tap coefficients into one optimization problem and allow them to collaborate and lead to the global optimal solution. The proposed joint optimization method is fast, easy to implement and efficient. The method has been tested for several measured channels and the analysis of the results are discussed.

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“…To meet the increasing demand of data rate and overcome the bandwidth limitation of channel, PAM4 (4-level Pulse Amplitude Modulation) signaling [1][2], as an alternative of NRZ (non-return-to-zero), has drawn more and more attention in highspeed serial link systems, especially for backplane applications. For example, it has been adopted for some aspects of the 400 Gb/s Ethernet standard [3].…”

Section: Introductionmentioning

confidence: 99%

IBIS-AMI Based PAM4 Signaling and FEC Technique for 25 Gb/s Serial Link

Zhan¹,

Hu²,

Zhang³

2017

Lecture Notes in Computer Science

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This paper investigates Input/Output Buffer Information Specification Algorithmic Model Interface (IBIS-AMI) model extension for 25Gb/s PAM4 (4-level Pulse Amplitude Modulation) serial link to improve the development efficiency. By using the ADS (Advanced Design System) Channel Simulator, the effects of device package, jitter and crosstalk on the actual performance are studied at first. Then, for forward error correction (FEC) technique, the bit error rate (BER) performance and the bathtub curves are analyzed in detail. Simulation results show that device package, jitter and crosstalk can make the link performance worse. And much better performance can be obtained by using the combination of equalization and FEC techniques compared with using the equalization technique separately.

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PAM4 signaling considerations for high-speed serial links

Cited by 13 publications

References 5 publications

A 50Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation

A 50Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation

Analytical method for joint optimization of FFE and DFE equalizations for multi-level signals

IBIS-AMI Based PAM4 Signaling and FEC Technique for 25 Gb/s Serial Link

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