Parallel pattern fault simulation of path delay faults

Abstract

This paper presents an accelerated fault simulation approach for path delay faults. The distinct features of the proposed fault simulation method consist in the application of parallel processing of patterns at all stages of the calculation procedure, its versatility to account for both robust and non-robust detection of path delay faults, and its capability of efficiently maintaining large numbers of path faults to be simulated.

Path hashing to accelerate delay fault simulation

“…The improvements and new techniques described in this paper are based on the robust path delay fault simulation of Smith [2] and its extension to nonrobust simulation introduced by S c h ulz et al [6].…”

“…Each v alue consists of the nal boolean value f0; 1g and the detectability status fs; p; g. A detectability status s indicates that a signal remains stable at its nal value, p shows that there is at least one path from a primary input that is path delay fault testable, and indicates that the detectability status of a signal is neither s nor p. The value propagation table for an OR gate and an inverter are shown in Table 1. Analogous propagation tables can be derived for AND and XOR gates [2,6]. _ 0s 1s 0p 1p 0 1 0s 0s 1s 0p 1p 0 1 1s 1s 1s 1s 1s 1s 1s 0p 0p 1s 0p 1 0p 1 1p 1p 1s 1 1 1 1 0 0 1s 0p 1 0 1 1 1 1s 1 1 1 1 : 0s 1s 1s 0s 0p 1p 1p 0p 0 1 1 0 Table 1: Robust propagation table for OR-and NOT-gates Schulz et al [6] showed that it is possible to collapse the six values to four values, if only nonrobust fault detection is required.…”

“…Analogous propagation tables can be derived for AND and XOR gates [2,6]. _ 0s 1s 0p 1p 0 1 0s 0s 1s 0p 1p 0 1 1s 1s 1s 1s 1s 1s 1s 0p 0p 1s 0p 1 0p 1 1p 1p 1s 1 1 1 1 0 0 1s 0p 1 0 1 1 1 1s 1 1 1 1 : 0s 1s 1s 0s 0p 1p 1p 0p 0 1 1 0 Table 1: Robust propagation table for OR-and NOT-gates Schulz et al [6] showed that it is possible to collapse the six values to four values, if only nonrobust fault detection is required. The detectability stati s and are merged to the new status p. The corresponding tables for propagating these values through an OR gate or an inverter are given in Table 2.…”

“…The path tree introduced in [6] has turned out to be time and space expensive for large path sets. We use the method of [12] t o guarantee ecient path handling.…”

“…Furthermore, they extended the approach to non-robust detection of path delay faults and they proposed a data structure to store the tested paths. Based on these two approaches various fault simulators for combinational [6,7] and sequential [8, 9 , 1 0 , 11] circuits have been proposed.…”