Parameter extraction of nano-scale MOSFETs using modified Y function method

Narasimhamoorthy, S.; Ghibaudo, G.; Mouis, M.

doi:10.1109/essderc.2010.5618348

Cited by 5 publications

(1 citation statement)

References 11 publications

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“…To separate the channel from the access resistance, we utilized the Y-function method, plotting the Y parameter versus V gs , as suggested by equation (3) (figure 3(b)) [32][33][34]:…”

Section: Electrical Characteristicsmentioning

confidence: 99%

Soft-type trap-induced degradation of MoS₂ field effect transistors

et al. 2018

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The practical applicability of electronic devices is largely determined by the reliability of field effect transistors (FETs), necessitating constant searches for new and better-performing semiconductors. We investigated the stress-induced degradation of MoS multilayer FETs, revealing a steady decrease of drain current by 56% from the initial value after 30 min. The drain current recovers to the initial state when the transistor is completely turned off, indicating the roles of soft-traps in the apparent degradation. The noise current power spectrum follows the model of carrier number fluctuation-correlated mobility fluctuation (CNF-CMF) regardless of stress time. However, the reduction of the drain current was well fitted to the increase of the trap density based on the CNF-CMF model, attributing the presence of the soft-type traps of dielectric oxides to the degradation of the MoS FETs.

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“…To separate the channel from the access resistance, we utilized the Y-function method, plotting the Y parameter versus V gs , as suggested by equation (3) (figure 3(b)) [32][33][34]:…”

Section: Electrical Characteristicsmentioning

confidence: 99%

Soft-type trap-induced degradation of MoS₂ field effect transistors

et al. 2018

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Modeling and Understanding the Compact Performance of h‐BN Dual‐Gated ReS₂ Transistor

Lee

Choi

Kaczer

et al. 2021

Adv Funct Materials

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In this study, high‐performance few‐layered ReS2 field‐effect transistors (FETs), fabricated with hexagonal boron nitride (h‐BN) as top/bottom dual gate dielectrics, are presented. The performance of h‐BN dual gated ReS2 FET having a trade‐off of performance parameters is optimized using a compact model from analytical choice maps, which consists of three regions with different electrical characteristics. The bottom h‐BN dielectric has almost no defects and provides a physical distance between the traps in the SiO2 and the carriers in the ReS2 channel. Using a compact analyzing model and structural advantages, an excellent and optimized performance is introduced consisting of h‐BN dual‐gated ReS2 with a high mobility of 46.1 cm2 V−1 s−1, a high current on/off ratio of ≈106, a subthreshold swing of 2.7 V dec−1, and a low effective interface trap density (Nt,eff) of 7.85 × 1010 cm−2 eV−1 at a small operating voltage (<3 V). These phenomena are demonstrated through not only a fundamental current–voltage analysis, but also technology computer aided design simulations, time‐dependent current, and low‐frequency noise analysis. In addition, a simple method is introduced to extract the interlayer resistance of ReS2 channel through Y‐function method as a function of constant top gate bias.

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