Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach

Zhang, Lihong; Jangkrajarng, N.; Bhattacharya, Sambuddha; Shi, C.-J. Richard

doi:10.1109/tcad.2008.917594

Cited by 33 publications

(21 citation statements)

References 20 publications

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“…We can roughly categorize them into two major stages, placement and routing. At the placement stage, certain approaches mainly focus on fully mapping [4], [2], [5], [6], [7], [3]. First of all, Bhattacharya et al in [4] detect the symmetric components from the source layout hierarchically and retarget it.…”

Section: A Previous Workmentioning

confidence: 99%

“…In [5], Bhattacharya et al extend the compaction to larger analog design as the multi-level layout generation. Moreover, in [6], Zhang et al deal with the parasitic effects as well as retargeting the compaction-based layout. Wang et al build template for analog layouts and then use geometric programming to guarantee the global optimal solution for compaction in [3].…”

Section: A Previous Workmentioning

confidence: 99%

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A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation

Pan

Chin

Chen

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Analog layout generation in the advanced CMOS design is challenging by its increasing layout constraints and performance requirements. This situation becomes more intricate by the growing parasitic variability and manufacturing reliability. To facilitate the feasibility of template-based layout migration, this paper firstly introduces a layout preservation, which extracts placement and routing behaviors from an existing layout into a crossing graph via constrained Delaunay triangulation (CDT). And later this crossing graph can be migrated into multiple layouts with placement and routing reconnection. The proposed approach also provides a refinement for wire to optimize the performance metrics. This approach is applied to a variablegain amplifier (VGA), a folded-cascode operational amplifier (OpAmp) and a low dropout regulator (LDO). The experimental results demonstrate more possibility on layout migration, such that averagely more than 75% routing of migrated layout is generated by our approach. Additionally, it exhibits the productivity with qualified performance on different designs.

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Section: A Previous Workmentioning

confidence: 99%

Section: A Previous Workmentioning

confidence: 99%

A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation

Pan

Chin

Chen

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Their formulation, although general, is less efficient since a linear programming solver has to be invoked to verify if a perturbed solution is acceptable. Nevertheless, this work fits naturally into the framework of template-driven analog layout re-targeting and optimization, an increasingly important area of research [24,25]. …”

Section: Prior Work and Our Focusmentioning

confidence: 99%

Symmetry‐aware placement algorithm using transitive closure graph representation for analog integrated circuits

Zhang

Jiang

et al. 2008

Circuit Theory & Apps

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SUMMARYRecently several topological representations have been explored as alternatives to the conventional absolute-coordinate representation for integrated circuit layout automation. Those topological representations, however, lack one or more aspects in capturing the solution space subject to symmetry constraints, which are abundant in analog layouts.In this paper, we explore the use of transitive closure graphs (TCGs) to represent analog placements, i.e. placements with symmetry constraints. We define a set of conditions so that a TCG satisfying these conditions, referred to as a symmetric-feasible TCG, will correspond to a valid symmetric placement and vice versa. We then present an O(n 2 ) algorithm, where n is the number of cells to be placed, to build a symmetric placement from a symmetric-feasible TCG, a problem known as packing.We further describe a set of random perturbation operations on existing symmetric-feasible TCGs to generate new symmetric-feasible TCGs with time complexity of O(n). This allows our TCG-based symmetry-aware analog placer to search only the symmetric-feasible TCG solution space, leading to a substantial reduction of the search space and solution time. Experimental results on several analog circuits have confirmed the superiority of the TCG representation to the conventional absolute-coordinate representation as well as several other topological representations in analog layout design.

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“…One of major reasons that designing an analog circuit is timeconsuming is because analog circuits are usually very sensitive to layout-induced parasitic effects [1]. Specifically, if parasitic effects are not considered early in an analog integrated circuit design flow, the problem of numerous redesign iterations (each of which includes processes of circuit sizing, layout generation, design-rule checking, parasitic extraction, and post-layout simulation) can arise [2].…”

Section: Introductionmentioning

confidence: 99%

Fast partitioning of parameterized 45-degree polygons into parameterized trapezoids

Tseng

Huang

et al. 2013

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)

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In this paper, an approach to the partitioning of parameterized 45-degree polygons into parameterized trapezoids by using horizontal cuts is proposed. In the process of partitioning a parameterized 45-degree polygon, the proposed approach invokes a mixed integer linear programming solver only once and can rapidly obtain results of comparing linear expressions. Compared with previous partitioning programs, the program implementing the proposed approach is very efficient and can achieve more than 100x speed-up while partitioning large parameterized polygons or parameterized polygons with complex constraints. The approach can be used as the basis to build trapezoidal corner stitching data structures for parameterized 45-degree layouts so that models of layout-induced parasitics can be generated automatically.

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Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach

Cited by 33 publications

References 20 publications

A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation

A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation

Symmetry‐aware placement algorithm using transitive closure graph representation for analog integrated circuits

Fast partitioning of parameterized 45-degree polygons into parameterized trapezoids

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