PCHECK: a delay analysis tool for high performance LSI design

Calculating worst-case gate delays due to dominant capacitance coupling

“…In [9] the RC load was modeled from the t α f α t in C L , ( ) = driving point admittance point of view as a π-circuit, while the input signal was represented by three parameters. This approach increases the number of SPICE runs required for characterization to very high levels (for example, from 16 to 4096 when considering every parameter sampled in 4 points).…”

“…Therefore, (9) where Z ji (s) is the transimpedance from node j to node i (Z ji (s)=Z ij (s) since the RC circuits are reciprocal). It should be noted that the average voltage principle is mathematically equivalent to the current averaging principle in [3].…”

Weibull based analytical waveform model

“…An accurate four parameter model for signal waveforms has been presented in [3] but it increases pre-characterization complexity by requiring a 4-dimensional table to store input information for gate instead of the one-dimensional table required for a ramp approximation. A 2-ramp model has been presented in [4] and it provides good accuracy for most of the signals. However, the model is hard to use because of its piecewise description and there is no clear deterministic method to determine when the model is applicable.…”