Peracetic Acid as Active Species in Mixtures for Selective Etching of SiGe/Si Layer Systems – Aspects of Chemistry and Analytics

Guder, Mathias; Kolbesen, Bernd O.; Delattre, Cécile; Schier, Herbert; Wagner, G.

doi:10.4028/www.scientific.net/ssp.134.79

Cited by 3 publications

(3 citation statements)

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“…Here, PAA is a product of the reaction between acetic acid and hydrogen peroxide: This reaction is catalyzed by strong acids such as HF or H 2 SO 4 . In the case of SiGe, HF also etches Si and Ge oxides. , Despite being the most common etchant for SiGe, very little is known about the details of the etch chemistry of HF:H 2 O 2 :CH 3 COOH:H 2 O and the etchant parameters that determine the etch rates. ,,− Also, earlier studies of etch chemistries for SiGe and Si focused on bulk structures ,,,,, and the details of etching of sub-100-nm SiGe nanostructures, which are essential for transistor fabrication, are largely unexplored. Moreover, the presence of two oxidizing agents (H 2 O 2 and PAA) in these solutions further complicates the identification of the underlying etch mechanisms, and it is unclear how the two oxidizing agents will work in tandem during the etching.…”

Section: Resultsmentioning

confidence: 99%

Selective Wet Etching of Silicon Germanium in Composite Vertical Nanowires

Baraissov

Pacco

Koneti

et al. 2019

ACS Appl. Mater. Interfaces

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Silicon Germanium (SixGe1-x or SiGe) is an important semiconductor material for the fabrication of nanowire-based gate-all-around transistors in the next-generation logic and memory devices. During the fabrication process, SiGe can either be used as a sacrificial layer to form suspended horizontal Si nanowires or, because of its higher carrier mobility, SiGe can also be used as a possible channel material that replaces Si in both horizontal and vertical nanowires. In both cases, there is a pressing need to understand and develop nanoscale etching processes that enable controlled and selective removal of SiGe with respect to Si. Here, we developed and tested solution-based selective etching processes for SiGe in composite (SiNx/Si0.75Ge0.25/Si) vertical nanowires. The etching solutions were formed by 2 mixing acetic acid (CH3COOH), hydrogen peroxide (H2O2), and hydrofluoric acid (HF). Here, the two chemicals (H2O2 and CH3COOH) react to form highly oxidizing peracetic acid (PAA or). The hydrofluoric acid serves both as a catalyst for PAA formation and as an etchant for oxidized SiGe. Our study shows that an increase in either of the oxidizer concentrations increases the etch rate, and the fastest etch rate of SiGe is associated with the highest PAA concentration. Moreover, using in situ liquid phase TEM imaging, we tested the stability of nanowires during wet etching and identified that SiGe/Si interface to be the weakest plane; we found that once the diameter of the 160-nm-tall Si0.75Ge0.25 nanowire reaches ~15 nm during the etching, the nanowire breaks at or very close to this interface. Our study provides an important insight into the details of the wet etching of SiGe and some of the associated failure modes that are becoming extremely relevant for the fabrication processes as the size of the transistors shrink with every new device-generation.

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Section: Resultsmentioning

confidence: 99%

Selective Wet Etching of Silicon Germanium in Composite Vertical Nanowires

Baraissov

Pacco

Koneti

et al. 2019

ACS Appl. Mater. Interfaces

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“…Then, the superlattice structure was patterned and etched down to the Si substrate by Inductive Coupled Plasma (ICP) to form a channel region as well as the S/D region. Moreover, the Si 0.7 Ge 0.3 sacrificial layers were selectively removed through etching solutions including 10% HF, 30% H 2 O 2 and 99.8% CH 3 COOH (mixing and aging for 72 h) with volume ratios of 1:2:3 [ 24 , 25 , 26 , 27 ]. After completing the suspended Si nanosheets using critical point drying, inter-layer (IL) formation and gate stack deposition of 3 nm HfO 2 and 10 nm TiN by Atomic Layer Deposition (ALD) were completed immediately afterwards.…”

Section: Stacked Gaa Nanosheets Fabrication and Discussionmentioning

confidence: 99%

Impact of Stress and Dimension on Nanosheet Deformation during Channel Release of Gate-All-Around Device

et al. 2023

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In this paper, nanosheet deformation during channel release has been investigated and discussed in Gate-All-Around (GAA) transistors. Structures with different source/drain size and stacked Si nanosheet lengths were designed and fabricated. The experiment of channel release showed that the stress caused serious deformation to suspended nanosheets. With the guidance of the experiment result, based on simulation studies using the COMSOL Multiphysics and Sentaurus tools, it is confirmed that the stress applied on the channel from source/drain plays an important role in nanosheet deformation during the fabrication process. The deformation of Si nanosheets would cause a serious degradation of the device performance due to an inability to control the work function of the metal gate. This study proposed that the uniformly stacked GAA nanosheets structure could be successfully demonstrated with suitable channel stress engineering provided by fitting S/D size and an appropriate channel length. The conclusions provide useful guidelines for future stacked GAA transistors’ design and fabrication.

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“…z E-mail: b.hollaender@fz-juelich.de in time, starting with a low etch rate for a freshly prepared solution and reaching a higher and constant etch rate after 48 h. Aging is necessary to obtain a stable equilibrium of the concentrations of H 2 O 2 , CH 3 COOH, and their reaction product peracetic acid, which acts as the oxidizing species. 16 For the study of the lateral etching speed and selectivity, SiGe/Si staircase heterostructures were epitaxially grown on Si͑100͒ and then patterned by lithography and anisotropic etching. In this case, the etching efficiency was measured employing cross-sectional scanning electron microscopy ͑SEM͒.…”

Section: Methodsmentioning

confidence: 99%

Wet Chemical Etching of Si, Si[sub 1−x]Ge[sub x], and Ge in HF:H[sub 2]O[sub 2]:CH[sub 3]COOH

Holländer

Buca

Mantl

et al. 2010

J. Electrochem. Soc.

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Device concepts are applied to strained layers ranging from pure Si to pure Ge to achieve higher carrier mobilities. Strain is generated by growth on Si1−xGex buffer layers with an appropriate Ge content. Processing of these heterostructures requires selective removal of individual layers. Different approaches to the etch Si, Si1−xGex , and Ge layers have been evaluated in terms of the etch rate, selectivity, and isotropy. All investigated etching methods used highly selective chemical etching solutions composed of HF, hydrogen peroxide, and acetic acid (HF:normalH2normalO2:CH3COOH) . The effect of the different HF content on the etch rate of pure Si, pure Ge, and Si1−xGex alloys with Ge mole fractions between 20 and 75% is presented. In general, the etch rate increases significantly with the increase in Ge content. As an example, the etch rate increases by a factor of more than 100 when the Ge content increases from 20 up to 75 atom %.

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Peracetic Acid as Active Species in Mixtures for Selective Etching of SiGe/Si Layer Systems – Aspects of Chemistry and Analytics

Cited by 3 publications

References 0 publications

Selective Wet Etching of Silicon Germanium in Composite Vertical Nanowires

Selective Wet Etching of Silicon Germanium in Composite Vertical Nanowires

Impact of Stress and Dimension on Nanosheet Deformation during Channel Release of Gate-All-Around Device

Wet Chemical Etching of Si, Si[sub 1−x]Ge[sub x], and Ge in HF:H[sub 2]O[sub 2]:CH[sub 3]COOH

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