Performance analysis of FPGA based Sobel edge detection operator

Yasri, Indra; Hamid, Nor Hisham; Yap, V.V.

doi:10.1109/iced.2008.4786751

Cited by 48 publications

(22 citation statements)

References 7 publications

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“…Base on the result of hardware accelerator architecture simulation shows significantly reduction on memory bandwidth access compare to the referenced architecture [5] as shown at table 3 below: The referenced architecture [5] Pixel read 5ns (25%) 20ns Pixel write 5ns (25%) 20ns Pixel read for derivative computation…”

Section: Resultsmentioning

confidence: 96%

“…This performance is achieved with the modification on referenced [5] architecture. The modification is performed on data pixel read, to include parallelism on the reading pixel data from memory.…”

Section: Ns (30%) 50nsmentioning

confidence: 96%

“…The paper presents an edge detection hardware accelerator to expedite the edge detection computation using the technique of memory bandwidth reduction. The increase of computation speed is significant compared to preliminary work [5].…”

Section: Introductionmentioning

confidence: 93%

“…The memory bandwidth reduction is achieved by parallelism in reading and pipelining in processing of derivative computation as referring to the concept in [12]. This method manages to achieve 75% memory bandwidth reduction compared to the preliminary architecture [5]. The original and derivative images are stored in the memory with 32 bits wide image data has an individual address.…”

Section: Hardware Accelerator Architecturementioning

confidence: 99%

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Real-time video edge detection with the memory access improvement

Yasri

Hamid

Yap

2010

2010 International Conference on Intelligent and Advanced Systems

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Real-time video processing is the basic requirement for applications such as video surveillance, traffic management and medical imaging. The high computation power is a requirement to support this operation. This requirement could be fulfilled by utilizing the hardware accelerator architecture for computation part. This paper presents the development of edge detection hardware accelerator architecture for real time video processing systems. The algorithm of Sobel edge detection operator is used to develop this hardware accelerator. The NTSC standard definition video is digitized at 720x480 with a video rate of 30 frames per second. To develop hardware accelerator datapath architecture the management of memory access is deployed and architecture based pipeline are made with the potential of improvements in acceleration to read the data pixel from memory. In addition, a finite state machine is used to ensure the hardware accelerator controls the sequence of derivative computation, write and read operations. Initial simulation shows that the hardware accelerator architecture manages to achieve approximately 75% memory bandwidth reduction compare to previous work [5].

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Section: Resultsmentioning

confidence: 96%

Section: Ns (30%) 50nsmentioning

confidence: 96%

Section: Introductionmentioning

confidence: 93%

Section: Hardware Accelerator Architecturementioning

confidence: 99%

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Real-time video edge detection with the memory access improvement

Yasri

Hamid

Yap

2010

2010 International Conference on Intelligent and Advanced Systems

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“…Edges consist of meaningful features and contained significant information. It's reduce significantly the amount of the image size and filters out information that may be regarded as less relevant, preserving the important structural properties of an image (Yuval, 1996) [2]. So this technique can be used in the field of image processing for object tracking and motion detection.…”

Section: Introductionmentioning

confidence: 99%

Area Efficient FPGA Implementation of Sobel Edge Detector for Image Processing Applications

Mehra¹,

Verma²

2012

IJCA

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In this Paper an efficient method of FPGA based design and implementation of area efficient Sobel Edge detection filter is presented using a combination of hardware and software components. The FPGA provides the necessary hardware for image processing algorithms with flexibility to support Sobel edge detection algorithm. A pipelined method is used to implement the edge detection filter. This approach is useful to improve the system performance by taking advantage of available look up tables, routing resources and shift registers available on target device. The proposed 2-D filter is designed using matlab, synthesized with Xilinx ISE 10.1 and implemented on Virtex II Pro based xc2vp30-7-FF896 FPGA device. Results show better performance of proposed design in terms of area utilization.

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Power and performance optimization in FPGA‐accelerated clouds

Tesfatsion

Proaño

Tomás

et al. 2018

Concurrency and Computation

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Energy management has become increasingly necessary in data centers to address all energy-related costs, including capital costs, operating expenses, and environmental impacts.Heterogeneous systems with mixed hardware architectures provide both throughput and processing efficiency for different specialized application types and thus have a potential for significant energy savings. However, the presence of multiple and different processing elements increases the complexity of resource assignment. In this paper, we propose a system for efficient resource management in heterogeneous clouds. The proposed approach maps applications' requirement to different resources reducing power usage with minimum impact on performance. A technique that combines the scheduling of custom hardware accelerators, in our case, Field-Programmable Gate Arrays (FPGAs) and optimized resource allocation technique for commodity servers, is proposed. We consider an energy-aware scheduling technique that uses both the applications' performance and their deadlines to control the assignment of FPGAs to applications that would consume the most energy. Once the scheduler has performed the mapping between a VM and an FPGA, an optimizer handles the remaining VMs in the server, using vertical scaling and CPU frequency adaptation to reduce energy consumption while maintaining the required performance. Our evaluation using interactive and data-intensive applications compare the effectiveness of the proposed solution in energy savings as well as maintaining applications performance, obtaining up to a 32% improvement in the performance-energy ratio on a mix of multimedia and e-commerce applications.

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Performance analysis of FPGA based Sobel edge detection operator

Cited by 48 publications

References 7 publications

Real-time video edge detection with the memory access improvement

Real-time video edge detection with the memory access improvement

Area Efficient FPGA Implementation of Sobel Edge Detector for Image Processing Applications

Power and performance optimization in FPGA‐accelerated clouds

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