Performance and Device Design Based on Geometry and Process Considerations for 14/16-nm Strained FinFETs

Rezali, Fazliyatul Azwa Md; Othman, N. A. F.; Mazhar, Maisarah; Hatta, Sharifah Fatmadiana Wan Muhamad; Soin, Norhayati

doi:10.1109/ted.2016.2520583

Cited by 39 publications

(17 citation statements)

References 44 publications

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“…1, which features a drain extension for the high voltage and a tri-gate for a short channel length. This device follows a simplified process flow, described in the bullet points in Fig 1, to form a typical 16 nm HKMG bulk FinFET on a p-type substrate [23]. In this process, a thin gate oxide composed of a 0.6 nm layer of SiO 2 and a 1.7 nm layer of HfO 2 is only deposited in the gate region.…”

Section: Device Structure and Conceptmentioning

confidence: 99%

On the Effects of High-K Dielectric RESURF in High-Voltage Bulk FinFETs

Cheng

Lai

et al. 2020

IEEE J. Electron Devices Soc.

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High-K dielectric reduced surface field (RESURF) effects in high-voltage bulk FinFETs through three-dimensional simulation are discussed in this paper for the first time. Compared to a planar gate LDMOSFET where the length of the drift region is the same, dielectric RESURF significantly increases the optimal implant dose for the drift region to a higher value, although BV 2 /R on,sp is similar. By using a high-K dielectric in the shallow trench isolation (STI) to further enhance the dielectric RESURF, the BV is increased and the R on,sp is reduced, yielding a significantly improved BV 2 /R on,sp , together with a better ON/OFF current ratio. However, with the insertion of the high-K STI, C GD is increased and a punch-through in the drift region caused by the depletion region occurs at a smaller V DS , which is consistent with theory. It is observed that the high-K dielectric RESURF also has an impact on the vertical breakdown, and care must be taken to achieve an optimal BV. The simulation results presented in this paper are of great importance for realizing a system-on-a-chip (SOC) based on advanced CMOS technologies.

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Section: Device Structure and Conceptmentioning

confidence: 99%

On the Effects of High-K Dielectric RESURF in High-Voltage Bulk FinFETs

Cheng

Lai

et al. 2020

IEEE J. Electron Devices Soc.

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“…Apart from doping concentration, the work function (WF) also plays an important role to tune the VTH value in junctionless MOSFETs [13,[26][27][28]. The WF significantly depends on the distribution of atoms at the surface of channel material, where a specific material has a fixed WF value [29]. Previously, the application of different metal-gate work functions in JLDGVM has been reported [22], stating that the ID of n-JLDGVM was increased as the WF was decreased.…”

Section: Metal-gate Work Function (Wf)mentioning

confidence: 99%

Geometric and process design of ultra-thin junctionless double gate vertical MOSFETs

Kaharudin¹,

Salehuddin²,

Zain³

et al. 2019

IJECE

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The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF.

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“…The JLSDGM device with HKMG emulates like it has a thinner oxide in inversion with associated improved capacitance that subsequently results in significant I ON improvements. Furthermore, the reduction in L g cause high average stress across the channel due to much smaller channel region [48]. The application of strained channel is aimed to boost the electron mobility with high doping concentration, thus leading to higher on-current [49].…”

Section: Fig 5 Plot Of On-current Versus Gate Lengthmentioning

confidence: 99%

Design Consideration and Impact of Gate Length Variation on Junctionless Strained Double Gate MOSFET

2019

IJRTE

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Aggressive scaling of Metal-oxide-semiconductor Field Effect Transistors (MOSFET) have been conducted over the past several decades and now is becoming more intricate due to its scaling limit and short channel effects (SCE). To overcome this adversity, a lot of new transistor structures have been proposed, including multi gate structure, high-k/metal gate stack, strained channel, fully-depleted body and junctionless configuration. This paper describes a comprehensive 2-D simulation design of a proposed transistor that employs all the aforementioned structures, named as Junctionless Strained Double Gate MOSFETs (JLSDGM). Variation in critical design parameter such as gate length (L g ) is considered and its impact on the output properties is comprehensively investigated. The results shows that the variation in gate length (L g ) does contributes a significant impact on the drain current (I D ), on-current (I ON ), off-current (I OFF ), I ON /I OFF ratio, subthreshold swing (SS) and transconductance (g m ). The JLSDGM device with the least investigated gate length (4nm) still provides remarkable device properties in which both I ON and g m (max) are measured at 1680 µA/µm and 2.79 mS/µm respectively. Engineering (FKEKK), UTeM. Her research interest includes process and device simulation of nanoscale MOSFETs device, advanced CMOS design, optimization approach (DOE) and process parameter variability. Z. A. F. M. Napiah received the B.Eng. degree in electrical engineering and the M.Eng. degree in Microelectronic from Universiti Teknologi Malaysia (UTM). He received the Ph.D. degree in Microelectronics from Kanawa University, Japan. He is currently a senior lecturer at Faculty of Electronic and Computer Engineering (FKEKK), UTeM. His research interest includes process and device simulation of MOSFET device, advanced CMOS design and CMOS based Photodetector and Photoreceiver.

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Performance and Device Design Based on Geometry and Process Considerations for 14/16-nm Strained FinFETs

Cited by 39 publications

References 44 publications

On the Effects of High-K Dielectric RESURF in High-Voltage Bulk FinFETs

On the Effects of High-K Dielectric RESURF in High-Voltage Bulk FinFETs

Geometric and process design of ultra-thin junctionless double gate vertical MOSFETs

Design Consideration and Impact of Gate Length Variation on Junctionless Strained Double Gate MOSFET

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