Performance Comparisons Between 7-nm FinFET and Conventional Bulk CMOS Standard Cell Libraries

Xie, Qing; Lin, Xue; Wang, Yanzhi; Chen, Shuang; Dousti, Mohammad Javad; Pedram, Massoud

doi:10.1109/tcsii.2015.2391632

Cited by 61 publications

(14 citation statements)

References 9 publications

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“…Nevertheless, a high reduction of the switching activity will lead to high dynamic power reduction. Considering that in the state-of-the-art Fin-FET technology the dynamic power dominates the static one [49], a high decrease of the dynamic power will compensate the static power of the approximate switches and eventually the total power consumption will decrease significantly. However, due to the added logic gates, the power increases when operating at the accurate level.…”

Section: Figurementioning

confidence: 99%

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Design Automation of Approximate Circuits With Runtime Reconfigurable Accuracy

2020

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Leveraging the inherent error tolerance of a vast number of application domains that are rapidly growing, approximate computing arises as a design alternative to improve the efficiency of our computing systems by trading accuracy for energy savings. However, the requirement for computational accuracy is not fixed. Controlling the applied level of approximation dynamically at runtime is a key to effectively optimize energy, while still containing and bounding the induced errors at runtime. In this paper, we propose and implement an automatic and circuit independent design framework that generates approximate circuits with dynamically reconfigurable accuracy at runtime. The generated circuits feature varying accuracy levels, supporting also accurate execution. Extensive experimental evaluation, using industry strength flow and circuits, demonstrates that our generated approximate circuits improve the energy by up to 41% for 2% error bound and by 17.5% on average under a pessimistic scenario that assumes full accuracy requirement in the 33% of the runtime. To demonstrate further the efficiency of our framework, we considered two state-of-the-art technology libraries which are a 7nm conventional FinFET and an emerging technology that boosts performance at a high cost of increased dynamic power. INDEX TERMS Approximate computing, approximate design automation, dynamically reconfigurable accuracy, low power.

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Section: Figurementioning

confidence: 99%

“…Power Model: The power consumption of a circuit can be approximated by the sum of the power consumption of the circuit's gates [49], [53]:…”

Section: B Proposed C-level Power and Error Evaluationmentioning

confidence: 99%

Design Automation of Approximate Circuits With Runtime Reconfigurable Accuracy

2020

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“…Various silicon and nonsilicon channel‐based transistors have been developed to pave the way for device scaling beyond Moore's law 8‐12 . The FinFET device with higher controllability over the gate region, improved I ON /I OFF ratio, mitigation of the threshold voltage variations by the elimination of the random dopant fluctuations, and the possibility of successful scaling to sub‐10‐nm technology nodes has been raised as a groundbreaking candidate for representing high‐performance ultrascaled VLSI circuits and systems 13,14 …”

Section: Introductionmentioning

confidence: 99%

“…[8][9][10][11][12] The FinFET device with higher controllability over the gate region, improved I ON /I OFF ratio, mitigation of the threshold voltage variations by the elimination of the random dopant fluctuations, and the possibility of successful scaling to sub-10-nm technology nodes has been raised as a groundbreaking candidate for representing high-performance ultrascaled VLSI circuits and systems. 13,14 Arithmetic blocks such as adders and multipliers are the most essential building blocks of the digital microprocessors and microsystems. Multipliers are one the most power-hungry units, which directly influence the overall performance of the computing systems.…”

Section: Introductionmentioning

confidence: 99%

Ultraefficient imprecise multipliers based on innovative 4:2 approximate compressors

Jooq

Ahmadinejad

Moaiyeri

2020

Circuit Theory & Apps

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SummaryThis study proposes two ultraefficient imprecise multipliers based on innovative 4:2 approximate compressor designs. The first proposed multiplier employs an ultracompact 8‐transistor 4:2 compressor to reduce the transistor count and energy dissipation. To improve the accuracy of the first proposed imprecise multiplier, the second multiplier also benefits from a semiaccurate 24‐transistor 4:2 approximate compressor for the high‐order bits. The 7‐nm fin field‐effect transistor (FinFET) technology, as one of the leading commercial technologies, is utilized to simulate the proposed multipliers in the environment. The simulation results indicate that the proposed imprecise multipliers show significant improvements regarding transistor count, delay, power, and power‐delay product as compared to their state‐of‐the‐art imprecise and exact counterparts. Along with the superior hardware efficiency, the MATLAB simulations demonstrate that the proposed multipliers also provide reasonable levels of accuracy. Moreover, a figure of merit (FOM) considering hardware efficiency and output quality is considered in order to evaluate the multipliers comprehensively. The FOM simulation results indicate that the proposed imprecise multipliers make a significant trade‐off between hardware efficiency and quality for approximate‐computing applications dealing with image multiplication.

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“…reach 0.75 V and 0.7 V for 10 nm and 7 nm respectively [5]. One of the approaches to reduce leakage current is the use of gate-source/drain underlap, but because it increases the series resistance R SD , it will apparently decrease the driving current [6], [7]. Equating the fin width to the gate length can suppress the SCEs without affecting the driving current as found in [8].…”

Section: Introductionmentioning

confidence: 99%

Low Leakage Current Symmetrical Dual-k 7 nm Trigate Bulk Underlap FinFET for Ultra Low Power Applications

et al. 2019

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The main purpose of this paper is to achieve as low as possible leakage current (I OFF) to meet the requirements for ultra-low power (ULP) applications. The proposed methodology is based on studying the effect of the most effective FinFET design parameters that directly impact its leakage current. The parameters explored in this paper are the effective channel lengths L eff , gate stacks, gate contact materials, and gatesidewall spacers (L sp). The results show that utilizing a symmetrical dual-k material for 7-nm underlap tri-gate FinFETs appreciably allows a sufficient ON current and low leakage current and hence low stand by power consumption. Specifically, the effect of spacer length L sp and L HK is investigated to get low leakage current keeping I ON /I OFF as high as possible. Moreover, the effective channel length in subthreshold conduction (L eff) is maintained greater than the gate length (L g) and the threshold voltage (V th) is adjusted by the proper metal gate work function. The performance of the proposed n-and p-FinFET devices is verified using Sentaurus TCAD simulator from Synopsys. The resulted I OFF is 17 pA/µ m for n-FinFET and 14.7 pA/µm for p-FinFET which are the lowest leakage currents found in recent publications. The achieved I ON /I OFF ratio for both proposed devices is found to be 12.3 × 10 6 and 11 × 10 6 , respectively, which are comparable to the published data. These parameters are obtained for an appropriate choice of L sp = 10 nm and L HK = 5 nm. In addition, the short channel effects variations with L HK have been investigated. INDEX TERMS 7 nm Bulk FinFET, leakage current, SymD-k spacer, TCAD, ultra-low power.

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Performance Comparisons Between 7-nm FinFET and Conventional Bulk CMOS Standard Cell Libraries

Cited by 61 publications

References 9 publications

Design Automation of Approximate Circuits With Runtime Reconfigurable Accuracy

Design Automation of Approximate Circuits With Runtime Reconfigurable Accuracy

Ultraefficient imprecise multipliers based on innovative 4:2 approximate compressors

Low Leakage Current Symmetrical Dual-k 7 nm Trigate Bulk Underlap FinFET for Ultra Low Power Applications

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