Performance Improvement of One-Transistor DRAM by Band Engineering

Pal, Ashish; Nainani, Aneesh; Gupta, Sakshi; Saraswat, Krishna C.

doi:10.1109/led.2011.2171912

Cited by 17 publications

(6 citation statements)

References 13 publications

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“…Progress beyond current CMOS technology, on the other hand, also needs materials that overcome silicon’s fundamental limitation of not enabling optical excitations due to an indirect band gap. So-called III/V semiconductors, mixtures of elements in the third and fifth main group of the periodic table, are highly promising, for example, for conducting channels − or even laser applications. , Monolithic integration of these materials with Si is desired to enable seamless integration with current CMOS technologies. This can be achieved with up-scalable growth techniques, specifically metal organic vapor phase epitaxy (MOVPE).…”

Section: Introductionmentioning

confidence: 99%

Pyramidal Structure Formation at the Interface between III/V Semiconductors and Silicon

et al. 2016

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An enhancement of computer performance following Moore’s law requires the miniaturization of semiconductor devices. Presently, their dimensions reach the nanoscale. Interfaces between materials become increasingly important as the volume is reduced. It is shown here how a pyramidal interface structure is formed irrespective of the conditions applied during the growth of two semiconductors. This drastically changes the common view of interfaces, which were assumed to be either atomically abrupt or interdiffused. Especially in semiconductor heteroepitaxy, a simple surface segregation of one atomic species is often assumed. It is proven by first-principles computations and kinetic modeling that the atom mobility during growth and the chemical environment at the interface are the decisive factors in the formation of the actual structure. Gallium phosphide grown on silicon was chosen as representative, nearly unstrained material combination to study the fundamental parameters influencing the interface morphology. Beyond that, this system has significant impact for cutting-edge electronic and optoelectronic devices. The findings derived in this study can be generalized to aid the understanding of further relevant semiconductor interfaces. This knowledge is crucial to comprehend current and steer future properties of miniaturized devices.

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Section: Introductionmentioning

confidence: 99%

Pyramidal Structure Formation at the Interface between III/V Semiconductors and Silicon

et al. 2016

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“…Galliumphosphide (GaP) layers on Si substrates have a device application by themselves, for example, in GaP/Si/GaP field-effect transistor (FET) stacks [74]. Aside from that, the direct device application of GaP/Si is limited, because of the indirect band structure of the GaP.…”

Section: Gap On Siliconmentioning

confidence: 99%

Growth of III/Vs on Silicon

Volz¹,

Stolz²,

Dadgar³

et al. 2015

Handbook of Crystal Growth

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“…The performance of QW structures can be enhanced by using GaP raised Source/Drain (RSD) regions [31], implementable in either planar SOI or FinFET process flow. For the same gate length, the RSD structure has higher volume to store the charge inside the body.…”

Section: Electron-hole Separationmentioning

confidence: 99%

Advanced Concepts for Floating-Body Memories

Gámiz

Rodríguez

Cristoloveanu

2012

Int. J. Hi. Spe. Ele. Syst.

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With 30nm-class memory cells in production and 20nm-class (20-29nm feature-size) memory targeted for next year, the standard 1-Transistor + 1-Capacitor (1T+1C) DRAM industry is making prominent efforts to improve the scalability of the cell capacitor while maintaining the minimum capacitance requirements for state discrimination, immune to noise (C~25fF/cell). To achieve the capacitance requirement, the DRAM cell has evolved from its initial planar implementation to complex three-dimensional structures. The increment in complexity and the large difference in size between the transistor and capacitor of each cell have motivated the search for Floating-Body Single-Transistor DRAM (1T-DRAM). The underlying idea behind 1T-DRAMs is the development of single-device memory cells with a pronounced hysteresis effect and fast operation. This chapter is focused on the floating-body effect as a primary source of hysteresis. We present new concepts able to deal with the basic limitations of 1T-DRAM while maintaining its simplicity. The floating-body 1T-DRAMs can be reconciled with the aggressive scaling constrains by considering new ideas which make possible the coexistence of electron and holes in the same ultrathin transistor. The best approach is to isolate each type of carrier in an specific potential well which is not created specifically by the bias conditions (unlike standard 1T-DRAMs) but by the physical structure of the device.

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Performance Improvement of One-Transistor DRAM by Band Engineering

Cited by 17 publications

References 13 publications

Pyramidal Structure Formation at the Interface between III/V Semiconductors and Silicon

Pyramidal Structure Formation at the Interface between III/V Semiconductors and Silicon

Growth of III/Vs on Silicon

Advanced Concepts for Floating-Body Memories

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