Perimeter effects in small geometry bipolar transistors

Lee, W.; Sun, J.Y.-C.; Warnock, J.; Jenkins, K.A.

doi:10.1109/vlsit.1992.200644

Cited by 2 publications

(1 citation statement)

References 1 publication

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“…To obtain high fT and highf,,,, not only implementing these techniques but also optimizing the impurity diffusion from the base-polysilicon electrode to the extrinsic base region are necessary. The large p+ diffusion from the polysilicon electrode increases base-collector junction capacitance and often causes massive degradation offT [5]. On the contrary, when the p+ diffusion is too small, base resistance increases drastically.…”

Section: Introductionmentioning

confidence: 99%

Very-high f/sub T/ and f/sub max/ silicon bipolar transistors using ultra-high-performance super self-aligned process technology for low-energy and ultra-high-speed LSI's

Ugajin¹,

Kodate²,

Kobayashi³

et al.

Proceedings of International Electron Devices Meeting

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andf,,, (up to 70 GHz) silicon bipolar transistors have been developed using Ultra-high-performance Super Self-aligned process Technology (USST). This technology is characterized by drastically-scaled lateral dimensions and shallow, heavilydoped extrinsic base, structures. USST greatly reduces base-collector junction capacitance and base resistance, and hence makes f,,, about twice as large as SSTlC [l] technology without vertical scaling. The fabricated ECL circuits show a minimum gate delay of 16.5 ps at a switching current of I, = 1.0 M G . 3 0 . 2 . 2 736-IEDM 95

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Section: Introductionmentioning

confidence: 99%

Very-high f/sub T/ and f/sub max/ silicon bipolar transistors using ultra-high-performance super self-aligned process technology for low-energy and ultra-high-speed LSI's

Ugajin¹,

Kodate²,

Kobayashi³

et al.

Proceedings of International Electron Devices Meeting

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Three-dimensional characterization of bipolar transistors in a submicron BiCMOS technology using integrated process and device simulation

Pinto

Boulin

Rafferty

et al. 1992

International Technical Digest on Electron Devices Meeting

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Results of complete 3-dimensional ac/dc characterizations of the npn transistor in a submicron BiCMOS technology are presented. Accuracy and throughput acceptable for constructing compact models is achieved through the use of multidimensional process simulation, adaptive grid generation and preconditioned iterative techniques for both dc and small-signal analysis. Comparisons of 2-and 3-dimensional simulations with measurements enable assessments of the magnitude of 3-dimensional effects, thereby suggesting efficient device optimization strategies.

show abstract

Perimeter effects in small geometry bipolar transistors

Cited by 2 publications

References 1 publication

Very-high f/sub T/ and f/sub max/ silicon bipolar transistors using ultra-high-performance super self-aligned process technology for low-energy and ultra-high-speed LSI's

Very-high f/sub T/ and f/sub max/ silicon bipolar transistors using ultra-high-performance super self-aligned process technology for low-energy and ultra-high-speed LSI's

Three-dimensional characterization of bipolar transistors in a submicron BiCMOS technology using integrated process and device simulation

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