The well-known expression equating the collector signal delay to one-half of the transit time through the base-collector depletion region is incorrect in the presence of a nonconstant carrier velocity, as occurs for velocity overshoot. The correct expression yields a smaller signal delay than the conventional estimate for typical situations, further emphasizing the benefit of velocity overshoot in bipolar devices. region (31, . Unfortunately, such an estimate for r,' is incorrect.The problem of computing .,' for nonuniform transit velocities has been considered in great detail in a somewhat analogous context, namely, the signal delay for electrons moving from cathode to anode in a vacuum tube [12]. The analogy is HE signal delay through the collector depletion region in a T bipolar transistor r,' is one term in the commonly used estimate for the common-emitter short-circuit unity-current-gain frequency fr = I / [2a(reCbe +reCbc +re +rb i-7,' + r c C b c ) ] [l], [2]. For scaled bipolar devices, r,' is becoming the dominant term in this sum. The usual way to estimate r,' is r,' = rc/2, where rc is the transit time across the base-collector depletion region. When the carrier velocity in the depletion region is nonuniform, this estimate is incorrect. For example, for the strongly nonuniform velocity profiles calculated for AlGaAdGaAs HBT's and shown in 13, fig. 81, this expression overestimates r,' by 20-60%, the largest errors occurring for the smallest transit times. This letter will present the correct expression, valid for nonuniform carrier velocities in the collector depletion region.The collector signal delay r,' is defined as the time delay in the collector transport factor l, which is a small-signal transfer function given by the ratio of the total current entering the collector depletion region from the base to the conduction current flowing at the same position. As originally stated by Early in the constant velocity approximation [4], By inspection of ( l ) , r,' = rc/2. For the constant velocity approximation, the transit time rc = x m /usat, where x m is the length of the depletion region and uSat is the carrier saturation velocity. Other derivations of this relationship have been given [5]-[7]. When carriers traverse the depletion region with a position-dependent velocity v ( x ) , 0 5 x 5 x m , it is tempting to compute the transit time as rc = J;m d x / v ( x ) , and simply set r,' = rc/2. Velocity overshoot is one situation where the velocity is expected to vary with position in the depletion Manuscript received January 16, 1990. The authors are with the IBM Research Division, Thomas J. Watson Re-IEEE Log Number 9034972. search Center, Yorktown Heights, NY 10598.clouded, however, by the origin of the position-dependent velocity: Newton's Law governs the acceleration of electrons in the vacuum tube, including space-charge effects. In the depletion region analysis, we simply fix v ( x ) a priori, independent of the field. In this sense the present problem is much easier, yet the methods in 1121 clarif...

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A novel bipolar isolation structure with capability of significantly reducing collector-base capacitance and base resistance is presented. Partial SOI, with SO1 surrounding the collector opening, can be used to reduce the collector window width in combination with any emitter-base self-aligned bipolar device structure, and in particular for device structures that feature sublithographic emitter width. Near-ideal transistor Gummel characteristics and a minimum ECL gate delay of 24 ps have been achieved with a nonoptimized lateral device layout, and simulations suggest that sub-20-ps delay at reduced switch current will be possible by using the optimized partial-SO1 isolation structure.

An epitaxial base bipolar technology has been used for fabrication of graded SiGe-base HBT's or Si-base pseudo-HBT's with a self-aligned, in-situ doped n-type low temperature epitaxial (LTE) emitter. The thin LTE emitter provides an EB junction with low tunnelling current and low capacitance in a n + poly/n/p + /n thin base HBT design with very high base doping. We report here on Si and SiGe devices utilizing a 40 nm P doped LTE emitter with an nf poly contact and silicided p + poly extrinsic base contact. Nearly ideal DC characteristics were obtained for a device with a peak base doping concentration of over 1 x 1019crn-3. 44 G H z~T devices with an AC base resistance of only 150 ohms were used to fabricate 24 ps ECL and 19 ps NTL ring oscillators to demonstrate the performance potential of the structure. BackgroundIn principle, the availability of high-quality Si-based low temperature epitaxy processes allows definition of arbitrarily thin basewidth transistors in a manner analogous to GaAs-based epitaxial technologies. Scaling to 30-40 nm basewidths in an n/p+ /n Si-based HBT technology, however, requires precise control of the emitter formation process with base doping (boron) concentrations in the 1 x 10'9 to 1 x 1OZ0crn-range. The emitter thermal cycle must be minimlzed to maintain a very narrow basewidth and the emitter doping concentration must be low enough to prevent excessive tunnelling while still being high enough to provide a low emitter resistance, minimize emitter charge storage, and prevent junction non-idealities associated with shallow polysilicon contacts. In a polysilicon emitter technology, however, formation of an n/p+ junction (as opposed to n+ /p) through reduction of the diffusion source concentration does not satisfy these criteria.GaAs-based epitaxial technologies typically employ an insitu doped single crystal emitter layer deposited immediately after base deposition to address the emitter doping problem and rely on the heterojunction effects to maintain adequate current gain. Direct extension of mesa type GaAs epitaxial structures for Si-based devices is not desirable, however, due to perimeter passivation, current gain, parasitic resistance, and narasitic capacitance concerns, and thus poor performance rel-..:ive to aggressive ion-implanted double-poly device structures. Over the last few years epitaxial base transistor structures have been proposed which address the isolation, resistance and capacitance related concerns noted above for an epitaxial technology and allow fabrication of high performance Si and SiGe base transistors in a double-poly process [1,2]. This work

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