Physical and timing verification of subwavelength-scale designs: I. Lithography impact on MOSFETs

Pack, Robert C.; Axelrad, V.; Shibkov, Andrei; Boksha, Victor V.; Huckabay, Judy; Salik, R.; Staud, Wolfgang; Wang, Ruoping; Grobman, W. D.

doi:10.1117/12.499089

Cited by 10 publications

(6 citation statements)

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“…There have been several approaches to electrically model non-rectilinear geometries [7][8][9][10][12][13][14]. All of these works consider the threshold voltage and hence the current density to be uniform along the device width.…”

Section: Introductionmentioning

confidence: 99%

Quantified Impacts of Guardband Reduction on Design Process Outcomes

Jeong

Kahng

Samadi

2008

9th International Symposium on Quality Electronic Design (Isqed 2008)

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A major source of patterning problems in low-k1 lithography is line-end pullback. Though geometric metrics such as CD at gate edge have served as good indicators, the ever-rising contribution of line-end extension to layout area necessitates reducing pessimism in qualifying line-end patterning. Electrically-aware metrics for line-ends can be helpful in this regard. In this work, we calculate the I on and I o f f impact of line-end taper shapes as well as line-end length. The proposed models are verified using TCAD simulation in a typical 65nm process. We observe that the device threshold voltage is a weak function of line-end pullback, and that the electrical impact of the taper can vary with overlay errors. We apply a non-uniform channel length model in addition to the proposed taper-dependent threshold voltage model to calculate ∆I on and ∆I o f f . Finally, the electrical metric for line-end printing is defined as expected change in I on or I o f f under a given overlay error distribution. We also propose a super-ellipse form to parameterize taper shapes, and then explore a large variety of taper shapes to characterize electrical impact.

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Section: Introductionmentioning

confidence: 99%

Quantified Impacts of Guardband Reduction on Design Process Outcomes

Jeong

Kahng

Samadi

2008

9th International Symposium on Quality Electronic Design (Isqed 2008)

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“…The currents for the fit can come from silicon data or silicon-based SPICE models. Average gate length models [6] do not account for short-channel effects, especially narrow width effects, which can contribute up to 25% more (or less) current per unit width than wide (greater than 1μm) transistors. In most 65nm library designs, all transistors could be considered narrow width, since the largest transistors may only be 0.5μm wide, with 0.2μm being a more typical NMOS width.…”

Section: Contour-based Transistor Modelingmentioning

confidence: 99%

Modeling and Validation of Silicon Contour-Based Extraction and Simulation of Non-Uniform Devices

Devoivre

Rouse²,

Verghese³

et al. 2007

2007 IEEE Custom Integrated Circuits Conference

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A current density-based model that incorporates narrow width effects is proposed to predict the drawn current of transistors that exhibit non-uniform device geometry. A continuous, integrable, analytical model of current density that includes the details of stress, edge effects and dopant loss/pileup is first calibrated to silicon data or existing SPICE models. Using the active and poly contours of the actual transistor shape obtained from a lithography-like simulation with an enriched model or directly from SEM images, the current density model is integrated over the width of the transistor to obtain its drawn current. From this predicted current, equivalent transistor parameters for circuit simulation can be extracted. Comparison to Silicon drive current measurements of Poly T and Active T structures on a ST 65nm process show excellent correlation, with an average difference of less than 0.5% for active shapes and 0.8% for poly shapes.

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“…The single most important process factor impacting chip frequency and leakage current distributions is the gate electrode width in the channel region [5,6,7]. Gate CD control involves several sources of variability, including wafer-to-wafer, within-wafer, and within-die variability.…”

Section: Reduced Gate CD Variability Using Gdrmentioning

confidence: 99%

Low k 1 logic design using gridded design rules

Smayling

Liu²,

Cai³

2008

SPIE Proceedings

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Dimensions for 32nm generation logic are expected to be ~45nm. Even with high NA scanners, the k 1 factor is below 0.32. Gridded-design-rules (GDR) are a form of restricted design rules (RDR) and have a number of benefits from design through fabrication. The combination of rules and topologies can be verified during logic technology development, much as is done with memories. Topologies which have been preverified can be used to implement random logic functions with "hotspot" prevention that is virtually context-independent. Mask data preparation is simplified with less aggressive OPC, resulting in shorter fracturing, writing, and inspection times. In the wafer fab, photolithography, etch, and CMP are more controllable because of the grating-like patterns. Tela Canvas™ GDR layout was found to give smaller area cells than a conventional 2D layout style. Variability and context independence were also improved.

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Physical and timing verification of subwavelength-scale designs: I. Lithography impact on MOSFETs

Cited by 10 publications

References 0 publications

Quantified Impacts of Guardband Reduction on Design Process Outcomes

Quantified Impacts of Guardband Reduction on Design Process Outcomes

Modeling and Validation of Silicon Contour-Based Extraction and Simulation of Non-Uniform Devices

Low k 1 logic design using gridded design rules

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