Physical limitations and design for sub-0.1-?m MOS devices: Carrier velocity overshoot and performance fluctuation

Investigating the relationship between electron mobility and velocity in deeply scaled NMOS via mechanical stress

“…So (3) where are values with strain, and are unstrained. Thus, although determination of absolute values of in very short devices is difficult due to sensitivity to errors in and estimates, fractional change is accurately measurable.…”

“…To better understand these scaling trends, as well as to assess potential benefits of technology alternatives for improved mobility (e.g., thin-film SOI, strained silicon) it is important to explore experimentally the relationship between low-field effective inversion-layer mobility and near-source electron velocity in aggressively scaled high-performance bulk NMOS devices operating in saturation . Previous experimental investigations [3], [4] of the -relationship have employed silicon-on-insulator MOS structures with light-doped channels and gate oxides in the 4 nm (physical) range; the observed -dependencies may not apply to deep-sub100-nm bulk NMOS devices with high channel doping. Experimental demonstrations of strained silicon technology [5], [6] suggest that low-field mobility is important to sub100-nm bulk MOSFET performance.…”