Physics and Mitigation of Excess OFF-State Current in InGaAs Quantum-Well MOSFETs

Lin, Jianqiang; Antoniadis, D.A.; Alamo, J.A. del

doi:10.1109/ted.2015.2410292

Cited by 22 publications

(19 citation statements)

References 24 publications

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“…The CSDG MOSFET delivers a cylindrical capacitance between the gate and conducting material. There exists an oxide layer that acts as a dielectric material [47]. Hence, this setup constitutes a concentric cylindrical capacitor between the layers of the transistor [38,42].…”

Section: Current Modeling For Csdg Mosfetmentioning

confidence: 99%

Capacitive Modeling of Cylindrical Surrounding Double-Gate MOSFETs for Hybrid RF Applications

Gowthaman

Srivastava

2021

IEEE Access

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The advancements in semiconductor technology greatly impact the growth of hybrid VLSI devices and components. The nanometer technology has been possibly executed due to the enhancement of the scaling factor of the MOSFETs. Since the MOSFETs play a vital role in building dense devices, it also has several research insights with various semiconductor materials with high-ƙ dielectrics. The high-ƙ dielectric material in the place of the conventional oxide layer in the MOSFET design results in improved performance by reducing the Short Channel Effects (SCEs). In this research work, an analytical model of the lightly doped Cylindrical Surrounding Double-Gate (DG) MOSFET has been proposed. The capacitance modeling has been done for this cylindrical structure. This modeling has been analyzed for all operating regions of the transistors, capacitance estimation, and electrical field dependence on the capacitance. The results have been compared with the results derived from previous research and tabulated. This novel model occupies less area on the board, and routing is more accessible than the conventional DG MOSFET design. The overall results have been following the agreement in terms of accuracy, area tradeoff, and high speed, making the novel model suitable for high-frequency/RF hybrid applications.

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Section: Current Modeling For Csdg Mosfetmentioning

confidence: 99%

Capacitive Modeling of Cylindrical Surrounding Double-Gate MOSFETs for Hybrid RF Applications

Gowthaman

Srivastava

2021

IEEE Access

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“…This is equivalent to the introduction of positive fixed charge below the channel. In floating-body transistor designs, it has been observed that positive fixed charge beneath the channel results in degraded subthreshold characteristics in short III-V MOSFETs [3], [13] and FDSOI transistors [34]. This suggests that the appropriate transistor redesign might mitigate an SCE in future InGaAs QW-MOSFETs.…”

Section: Off-state Characteristicsmentioning

confidence: 99%

“…This has enabled the fundamental device physics studies of relevance for future logic. For example, we have recently identified the band-to-band tunneling amplified by a parasitic bipolar effect as the cause of excess OFF-state leakage current at high drain bias in InGaAs MOSFETs [12], [13]. Mitigating this is an important priority for future scaled InGaAs MOSFETs [7], [14], [15].…”

Section: Introductionmentioning

confidence: 99%

Impact of Intrinsic Channel Scaling on InGaAs Quantum-Well MOSFETs

Lin

Antoniadis

Alamo

2015

IEEE Trans. Electron Devices

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Using a novel gate-last process scheme that affords precise channel thickness control, we have fabricated self-aligned InGaAs quantum-well (QW) MOSFETs. Devices with a channel thickness between 3 and 12 nm, and a gate length between 40 nm and 5 µm are fabricated on a heterostructure that includes a composite InGaAs/InAs QW and an InP barrier. It is observed that channel thickness has a strong impact on the device characteristics. In general, a thick channel is beneficial to ON-state figures of merit, including transconductance and effective carrier mobility. However, a thin channel is beneficial to OFF-state metrics, such as subthreshold swing and drain-induced barrier lowering (DIBL). The InAs composition and effective mass that electrons experience in the channel emerges as a factor that significantly affects channel mobility and presumably the transport characteristics of these devices. The subthreshold swing and DIBL are found to follow a classic scaling behavior. This suggests that the InGaAs QW MOSFETs are at the limit of scaling around L g = 50 nm.Index Terms-III-V, MOSFETs, quantum-well (QW), self-aligned.

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“…Combining a high mobility channel material, such as InGaAs, with a vertical nanowire transistor geometry is particularly interesting as the VNW geometry opens the door to heterojunction engineering in the transport direction. This new design freedom, not possible in all other lateral transistor configurations, potentially offers significant advantages, such as a reduction in gate-induced drain leakage [5]. In addition, the relaxed gate length scaling that the VNW architecture enables can alleviate the direct source to drain tunneling that is prominent in InGaAs MOSFETs with ultra-scaled dimensions [6].…”

Section: Introductionmentioning

confidence: 99%