Poly-Si Nanowire TFT With Raised Source/Drain and Nitride Spacer

Reduction of Kink Effect of Poly-Si TFT With Bottom Field Plate by Dispersing Current Density Technique

“…2(d). It is noted that the maximum electric field always occurs on the top corner of the symmetric spacer channel TFT [13], [14]. Therefore, the bottom FP disperses the high current density away from the top corner of the spacer channel with a highest electric field for the proposed asymmetric TFT.…”

“…Regarding multiple-gate poly-Si TFTs with the spacer channels, the OFF-state leakage currents, ON/OFF current ratios, and kink effects were effectively improved by nitride spacer and vacuum structures [13], [14]. However, these structures still degraded ON-state current.…”

Clean-Induced Instability of Electrical Characteristics in Poly-Si Junctionless Nanowire Transistor

“…It is noted that the maximum electric field always occurs at the top corner of the spacer channel TFT. 13,14 Similarly, under OFF state, the electric field at drain region is higher in the SC1-5 NW TFT. The effect of the defects at grain boundaries and in the gate oxide on electrical characteristics should be clarified.…”

“…[8][9][10][11] An IM TFT with a "thicker" suspended spacer channel showed an excellent performance. [12][13][14] In our experiences, a JL transistor with a "very thin" suspended channel was easily broken in the wet bench and obviously affect its electrical characteristics. Therefore, the tri-gated JL transistor with a tiny channel adhered to a Si 3 N 4 film is a proposed structure in this paper.…”