Polynomial circuit models for component matching in high-level synthesis

Smith, James W.; Micheli, G. De

doi:10.1109/92.974892

Cited by 37 publications

(20 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, these tools lack the mathematical wherewithal to perform sophisticated algebraic manipulation for arithmetic datapath-intensive designs. Such designs implement a sequence of add, mult type of algebraic computations over bit-vectors; they are generally modeled at RTL or behavioral-level as systems of multi-variate polynomials of finite degree [3] [4]. Hence, there has been increasing interest in exploring the use of algebraic manipulation of polynomial expressions, for RTL synthesis of arithmetic datapaths.…”

mentioning

confidence: 99%

Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis

Gopalakrishnan

Kalla

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

View full text Add to dashboard Cite

Common sub-expression elimination (CSE) serves as a useful optimization technique in the synthesis of arithmetic datapaths described at RTL. However, CSE has a limited potential for optimization when many common sub-expressions are not exposed. Given a suitable transformation of the polynomial system representation, which exposes many common sub-expressions, subsequent CSE can offer a higher degree of optimization. The objective of this paper is to develop algebraic techniques that perform such a transformation, and present a methodology to integrate it with CSE to further enhance the potential for optimization. In our experiments, we show that this integrated approach outperforms conventional methods in deriving areaefficient hardware implementations of polynomial systems. I. IntroductionHigh-level descriptions of arithmetic datapaths that perform polynomial computations over bit-vectors are found in many practical applications, such as in Digital Signal Processing (DSP) for multi-media applications and embedded systems. These polynomial designs are initially specified using behavioural or Register-Transfer-Level (RTL) descriptions, which are subsequently synthesized into hardware using high-level/logic synthesis tools [1]. The growing market for such applications requires sophisticated CAD support for their design, optimization and synthesis.The general area of high-level synthesis has seen extensive research over the years. Various algorithmic techniques have been devised, and CAD tools have been developed that are quite adept at capturing hardware description language (HDL) models and mapping them into control/data-flow graphs (CDFGs), performing scheduling, resource allocation and sharing, binding, retiming, etc., [2]. However, these tools lack the mathematical wherewithal to perform sophisticated algebraic manipulation for arithmetic datapath-intensive designs. Such designs implement a sequence of add, mult type of algebraic computations over bit-vectors; they are generally modeled at RTL or behavioral-level as systems of multi-variate polynomials of finite degree [3] [4]. Hence, there has been increasing interest in exploring the use of algebraic manipulation of polynomial expressions, for RTL synthesis of arithmetic datapaths. Several techniques such as Horner decomposition, factoring with common sub-expression elimination [5], term-rewriting [6], etc., have been proposed. Symbolic computer algebra [3] [4] [7] has also been employed for

show abstract

mentioning

confidence: 99%

Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis

Gopalakrishnan

Kalla

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

View full text Add to dashboard Cite

show abstract

“…However, the derived polynomial models represent the computations over the fields of reals (R), fractions (Q) or over the integral domain (Z) -collectively called the unique factorization domains (UFDs). This often results in a polynomial approximation [3], without properly accounting for the effect of bit-vector size on the resulting computation. While the work of [9] does account for the datapath-size for allocation, it operates directly on the original (given) arithmetic expression -thus limiting the degree of freedom in searching for a better implementation.…”

mentioning

confidence: 99%

Optimization of Arithmetic Datapaths with Finite Word-Length Operands

Gopalakrishnan

Kalla

Enescu

2007

2007 Asia and South Pacific Design Automation Conference

View full text Add to dashboard Cite

This paper presents an approach to area optimization of arithmetic datapaths that perform polynomial computations over bit-vectors with finite widths. Examples of such designs abound in DSP for audio, video and multimedia computations where the input and output bit-vector sizes are dictated by the desired precision. A bit-vector of size m represents integer values reduced modulo 2 m (%2 m ). Therefore, finite wordlength bit-vector arithmetic can be modeled as algebra over finite integer rings, where the bit-vector size dictates the ring cardinality. This paper demonstrates how the number-theoretic properties of finite integer rings can be exploited for optimization of bit-vector arithmetic. Along with an analytical model to estimate the implementation cost at RTL, two algorithms are presented to optimize bit-vector arithmetic. Experimental results, conducted within practical CAD settings, demonstrate significant area savings due to our approach.I. Introduction RTL descriptions of integer datapaths that implement polynomial arithmetic are found in many practical applications, such as in digital signal processing (DSP) for audio, video and multimedia applications [1] [2]. Such designs perform a sequence of add, mult, shift type of algebraic computations over bit-vectors; hence they are generally modeled at RTL or behavioural-level as multi-variate polynomials of finite degree [2] [3]. Initial algorithmic specifications (such as a matlab model) of such systems involve data representation using floating-point formats. However, they are often implemented with fixed-point architectures in order to optimize the area, delay and power related costs of the implementation [4]. Subsequently, the fixedpoint model can be translated into an RTL description [5] -that can be subsequently synthesized into a circuit.Algebraic techniques and tools have been used for synthesis and optimization of such systems. However, for their efficient and correct modeling, it is important to account for the effect of bit-vector size of the operands on the resulting computation. In other words, a bit-vector of size m represents integer values from 0 to 2 m -1 (or integers reduced modulo 2 m ). This implies that finite word-length (m) bit-vector arithmetic manifests itself as algebra over finite integer rings (Z2m ). Properties of such finite rings should therefore be exploited for RTL optimization of bitvector arithmetic.This paper models finite word-length bit-vector arithmetic as polynomial functions (or polyfunctions) over f : Z 2 n 1 ×

show abstract

“…For high-level datapath verification, Smith and Micheli presented a polynomial method for component matching and verification and researched polynomials as allocating components [4,5]. Moreover, they found a polynomial model for component matching at a high synthesis level [6]. Based on their studies, numerous other research efforts were performed; for instance, the algorithms were proposed to achieve lower costs and minimum timing, driven in high-level data flow synthesis with symbolic algebra [7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Approximate Bisimulation for High-Level Datapaths in Intelligent Transportation Systems

Deng

Hui‐min

2013

Advances in Mechanical Engineering

View full text Add to dashboard Cite

A relation called approximate bisimulation is proposed to achieve behavior and structure optimization for a type of high-level datapath whose data exchange processes are expressed by nonlinear polynomial systems. The high-level datapaths are divided into small blocks with a partitioning method and then represented by polynomial transition systems. A standardized form based on Ritt-Wu's method is developed to represent the equivalence relation for the high-level datapaths. Furthermore, we establish an approximate bisimulation relation within a controllable error range and express the approximation with an error control function, which is processed by Sostools. Meanwhile, the error is controlled through tuning the equivalence restrictions. An example of high-level datapaths demonstrates the efficiency of our method.

show abstract

Polynomial circuit models for component matching in high-level synthesis

Cited by 37 publications

References 11 publications

Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis

Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis

Optimization of Arithmetic Datapaths with Finite Word-Length Operands

Approximate Bisimulation for High-Level Datapaths in Intelligent Transportation Systems

Contact Info

Product

Resources

About