Polysilicon encapsulated local oxidation

Roth, Sophie; Ray, W.; Mazuré, C.; Kirsch, H.C.

doi:10.1109/55.75722

Cited by 30 publications

(7 citation statements)

References 5 publications

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“…The samples used in this study were fabricated using a twin well split drive-in technology [3] and PELOX isolation [4]. n+ polysilicon gates were used with a nitride antireflection coating and a CVD-Oxide cap for deep sub-pm patterning.…”

Section: Methodsmentioning

confidence: 99%

Impact of LDD spacer reduction on MOSFET performance for sub- mu m gate/space pitches

Mazure

Gunderson

Роман

1992

International Technical Digest on Electron Devices Meeting

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The impact of very thin sidewall LDD spacers which are required to allow sub-pm gate/space pitches on MOSFETs is discussed for the first time. The effects of LDD spacer materials, LPCVD TEOS and nitride, on the device characteristics and short channel behavior of n and p-channel MOSFETs are analyzed. We show that the main issue related to sub-100nm spacers is gate-induced drain leakage and not device reliability. Nitride spacers improve device reliability and current drive but result in higher levels of gate-induced drain leakage. Our findings show that for sub-half pm devices, spacer thickness reduction down to 600A has no appreciable effect on lifetime.

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Section: Methodsmentioning

confidence: 99%

Impact of LDD spacer reduction on MOSFET performance for sub- mu m gate/space pitches

Mazure

Gunderson

Роман

1992

International Technical Digest on Electron Devices Meeting

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“…5 The 1T-Flash devices had 95 Å nitrided tunnel oxide with in situ doped floating gate poly of ϳ1500 Å thick, and the interpoly isolation was achieved with ϳ250 Å of oxide-nitride-oxide stack. The process uses ϳ3 m epi on a P ϩ substrate, coupled with advanced I-line lithography and PELOX isolation.…”

Section: Device Fabricationmentioning

confidence: 99%

Nonerratic behavior of overerased bits in flash EEPROM

Nkansah

Prinz

Hatalis

1998

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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We report the effects of flash “channel” programming, or severe gate disturb, on the threshold voltage of fast or overerased bits. Experiments have been performed to establish that this class of fast bits are nonerratic and remain fast after 250 °C bake. These fast bits exhibit identical subthreshold characteristics similar to that of a normal bit after ultraviolet erase, thus establishing that the initial charge stored on the floating gate is the same for both normal and fast bits. Polysilicon grain boundary enhanced electric fields which result in impact ionization by tunneling electrons, thus generating trapped positive charges in the grain boundary oxide ridges are believed to play an important role in the generation of fast bits.

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“…The width dependence can be explained in terms of three distinct regimes: merging of oxidant profiles for very narrow widths, coupling of nitride stresses for intermediate widths, and the large width regime which involves no interaction between the two nitride edges. (Obtained using PELOX isolation [3,4])…”

Section: Discussionmentioning

confidence: 99%

“…In order to generalize our results, we compared data for three different isolation schemes: Conventional LOCOS, Poly-Buffer LOCOS (PBL) [2], and PolyEncapsulated LOCOS (PELOX) [3,4].…”

Section: Methodsmentioning

confidence: 99%

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Sensitivity of field isolation profiles to active pattern

Kenkare

Pfiester

Hayden

et al.

Proceedings of IEEE International Electron Devices Meeting

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The birds beak profile for LOCOS-based isolations is shown to be a strong function of the patterned nitride width. In particular, the bird's beak height is found to be much smaller for intermediate widths (-0.6pm) than for either very wide or very narrow nitride lines. These width-dependent phenomena are explained using simulation. Furthermore, the use of Atomic Force Microscopy (AFM) is presented as a convenient approach for quantifying the 2-D encroachment effects common to all LOCOS-based schemes.

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Polysilicon encapsulated local oxidation

Cited by 30 publications

References 5 publications

Impact of LDD spacer reduction on MOSFET performance for sub- mu m gate/space pitches

Impact of LDD spacer reduction on MOSFET performance for sub- mu m gate/space pitches

Nonerratic behavior of overerased bits in flash EEPROM

Sensitivity of field isolation profiles to active pattern

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