Polysilicon thin-film transistors with channel length and width comparable to or smaller than the grain size of the thin film

Yamauchi, Noriyoshi; Hajjar, Jean-Jacques; Reif, R.

doi:10.1109/16.65736

Cited by 115 publications

(33 citation statements)

References 17 publications

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“…2) The devices must not latch up and a fast mechanism like drift, rather than recombination [10], must remove all the injected carriers when the device switches from the ON to the OFF state. 3) And finally, the most fundamental challenge arises from the understanding that there is a finite bandwidth associated with every gain mechanism and, depending on the magnitude of the gain desired, this gain-bandwidth product may impose fundamental limitations on "intrinsic" device switching speed.…”

mentioning

confidence: 99%

Impact Ionization MOS (I-MOS)—Part I: Device and Circuit Simulations

Gopalakrishnan

Griffin

Plummer

2005

IEEE Trans. Electron Devices

294

127

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Abstract-One of the fundamental problems in the continued scaling of transistors is the 60 mV/dec room temperature limit in the subthreshold slope. In part I this work, a novel transistor based on the field-effect control of impact-ionization (I-MOS) is explored through detailed device and circuit simulations. The I-MOS uses gated-modulation of the breakdown voltage of a p-i-n diode to switch from the OFF state to the ON state and vice-versa. Device simulations using MEDICI show that the I-MOS has a subthreshold slope of 5 mV/dec or lower and ON 1 mA m at 400 K. Simulations were used to further explore the characteristics of the I-MOS including the transients of the turn-on mechanism, the short-channel effect, scalability, and other important device attributes. Circuit mode simulations were also used to explore circuit design using I-MOS devices and the design of an I-MOS inverter. These simulations indicated that the I-MOS has the potential to replace CMOS in high performance and low power digital applications. Part II of this work focuses on I-MOS experimental results with emphasis on hot carrier effects, germanium p-i-n data and breakdown in recessed structure devices.Index Terms-Avalanche, avalanche photodiode (APD), gate control of impact ionization, impact-ionization avalanche transit-time (IMPATT), germanium, hot carriers, impactionization (I-MOS), kT/q, low static power, modulated breakdown, MOSFET, nonlinearity, p-i-n, silicon, subthreshold slope, 5 mV/dec.

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confidence: 99%

Impact Ionization MOS (I-MOS)—Part I: Device and Circuit Simulations

Gopalakrishnan

Griffin

Plummer

2005

IEEE Trans. Electron Devices

294

127

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“…Specifically we seek to explain more fully the conduction mechanism when a single GB is present than has been previously discussed [2], [3]and to investigate the effect on transistor performance. By comparing the subthreshold characteristics of the TFT with a silicon-on-insulator (SOI) equivalent device any differences due to the presence of the GB can be observed.…”

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confidence: 99%

Improved Off-Current and Subthreshold Slope in Aggressively Scaled Poly-Si TFTs With a Single Grain Boundary in the Channel

Walker

Mizuta

Uno

et al. 2004

IEEE Trans. Electron Devices

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Abstract-A polycrystalline-silicon thin-film transistor (TFT), with a single grain boundary (GB) present in the channel, is simulated using two-dimensional numerical simulation, which includes a model of deep trap states at GBs. It is observed that the potential barrier resulting from a GB in the channel acts to suppress current flowing through the channel when the barrier height is greater than the thermal voltage. The conduction mechanism in the subthreshold regime is clarified. The turn-on characteristics of the device are controlled primarily by gate-induced grain barrier lowering as opposed to modulation of carriers in the channel by the gate voltage. In the negative bias region it is found that suppression of the off current is aided by the GB potential barrier. Scaling of the various geometrical parameters of the device are investigated. Improved subthreshold characteristics, compared to an equivalent silicon-on-insulator (SOI) structure, are found for aggressively scaled devices, due to the presence of a GB in the channel.

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“…As demonstrated in Table 1, virgin X-directed TFTs exhibit almost identical electrical behavior in the linear regime of operation normalized to the channel width, indicating that narrow width effects may be neglected in this case [6,7]. Therefore, a common stress condition for these devices will allow a consistent comparison of hot-carrier stress degradation.…”

Section: Resultsmentioning

confidence: 90%