Polytypic InP Nanolaser Monolithically Integrated on (001) Silicon

Wang, Zhechao; Tian, Bin; Paladugu, Mohanchand; Pantouvaki, Marianna; Thomas, Nicolas Le; Merckling, Clément; Guo, Weiming; Dekoster, J; Campenhout, Joris Van; Absil, P.; Thourhout, Dries Van

doi:10.1021/nl402145r

Cited by 65 publications

(56 citation statements)

References 41 publications

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“…A possible explanation therefore is that the valence band splitting of the wurtzite-like InP crystal phase formed by the twins is responsible for this high photon energy emission peak 38,39 . From our previous work 40 and the reliable laser oscillation demonstrated in this work, we can conclude this InP crystal phase mixture does not comprise the material's quality for optoelectronic applications.…”

Section: Photoluminescence Study Of the Inp Epitaxially Grown On mentioning

confidence: 68%

“…But the few degrees miscut silicon substrate together with the thick III-V buffers needed to accommodate the lattice mismatch are not compatible with standard CMOS processes. Finally, also the growth of III-V nanowires on silicon is heavily studied 19,20 , but it is challenging to integrate these together with low loss optical waveguide circuits.Recently however the field of III-V epitaxy on silicon received a boost by the renewed interest of the electronics industry in using high mobility compound semiconductors in next generation CMOS 21,22 . Low defect density growth of GaAs 23 , InP 24,25 and InGaAs 26 compounds using selective area growth on prepatterned (001)-silicon was achieved, leading to the demonstration of the world's first III-V FinFET devices grown on a 300 mm substrate.…”

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Room-temperature InP distributed feedback laser array directly grown on silicon

et al. 2015

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These authors contributed equally to this work.Fully exploiting the silicon photonics platform requires a fundamentally new approach to realize high-performance laser sources that can be integrated directly using wafer-scale fabrication methods. Direct band gap III-V semiconductors allow efficient light generation but the large mismatch in lattice constant, thermal expansion and crystal polarity makes their epitaxial growth directly on silicon extremely complex. Here, using a selective area growth technique in confined regions, we surpass this fundamental limit and demonstrate an optically pumped InP-based distributed feedback (DFB) laser array grown on (001)-Silicon operating at room temperature and suitable for wavelength-division-multiplexing applications. The novel epitaxial technology suppresses threading dislocations and anti-phase boundaries to a less than 20nm thick layer not affecting the device performance. Using an in-plane laser cavity defined by standard top-down lithographic patterning together with a high yield and high uniformity provides scalability and a straightforward path towards cost-effective cointegration with photonic circuits and III-V FINFET logic.The potential of leveraging well-established and high yield manufacturing processes developed initially by the electronics industry has been the main driver fueling the massive research in silicon photonics over 2 the last decade [1][2][3][4][5][6] . From the start of its development though the lack of efficient optical amplifiers and laser sources monolithically integrated with the silicon platform inhibited the widespread adoption in high-volume applications. Solutions relying on flip-chipping prefabricated laser diodes 7,8 or bonding III-V epitaxial material [9][10][11] are now being deployed in commercially available optical interconnects but are less compatible with standard high-volume and low cost manufacturing processes. Approaches focusing on the engineering of group IV materials have achieved optical gain but still require extensive work to reach room temperature lasing at reasonable efficiency [12][13][14] . Therefore, the monolithic integration of direct bandgap III-V semiconductors, well known to be efficient light emitters, with the silicon photonics platform is heavily investigated. However, considerable hurdles need to be overcome. When directly growing III-V semiconductors on silicon substrates, the large lattice mismatch (εInP/Si = 8.06 %), the difference in thermal expansion and the different polarity of the materials result in large densities of crystalline defects including misfit and threading dislocations, twins, stacking faults and anti-phase boundaries, strongly degrading the performance and reducing the lifetime of any device fabricated in the as-grown layers 15 . Several routes to overcome these issues have been proposed. GaP-related materials can be grown on exact (001) silicon substrates with a small lattice mismatch and pulsed laser oscillation around 980 nm up to 120 K 16 has been achieved but shifting the laser...

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Section: Photoluminescence Study Of the Inp Epitaxially Grown On mentioning

confidence: 68%

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confidence: 99%

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Room-temperature InP distributed feedback laser array directly grown on silicon

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“…Moreover, we study the impact of the crystalline alignment of the InP layer with the underlying substrate by exploring as starting geometry at the bottom STI, i.e., rounded etch with Ge buffer 14,17 versus a crystalline h111i V-groove structure in the Si (Ref. 18) as shown in Figure 1(a).…”

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Heteroepitaxy of InP on Si(001) by selective-area metal organic vapor-phase epitaxy in sub-50 nm width trenches: The role of the nucleation layer and the recess engineering

Merckling

Waldron

Jiang

et al. 2014

Journal of Applied Physics

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This study relates to the heteroepitaxy of InP on patterned Si substrates using the defect trapping technique. We carefully investigated the growth mechanism in shallow trench isolation trenches to optimize the nucleation layer. By comparing different recess engineering options: rounded-Ge versus V-grooved, we could show a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. The demonstration of III-V heteroepitaxy at scaled dimensions opens the possibility for new applications integrated on Silicon.

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“…Therefore, there is a need for the integration of III-V semiconductors on silicon photonic integrated circuits, in order to complete the toolkit for the realization of complex and advanced heterogeneous silicon photonic integrated circuits. The integration of III-V semiconductor opto-electronic components onto silicon photonic integrated circuits can be realized in various ways, ranging from flip-chip integration [1] over bonding approaches [2][3][4] to hetero-epitaxial growth [5]. Flip-chip integration has the advantage that the devices can be grown and fabricated on their native substrate, while it does require accurate alignment in the assembly process.…”

Section: Introductionmentioning

confidence: 99%